Page Index - mbits-mirafra/digitalDesignCourse GitHub Wiki

257 page(s) in this GitHub Wiki:

• Home
• Welcome to the digitalDesignCourse wiki!
• digital design course layout
• 1.Binary Number System
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• Adders
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• Arithmetic circuits
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• Arithmetic circuits Page
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• Arithmetic Circuits using Sequential Design
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• Asynchronous counters
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• Asynchronous Flip Flop
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• ASYNCHRONOUS INPUT T FLIP FLOP
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• Bcd Adder
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• Binary adder subtractor
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• BINARY AND GRAY CODE
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• Binary Divider
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• Binary Number System
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• Blocking & Nonblocking Assignments
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• Boolean Algebra
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• Boolean minimization using K map and Quine McCluskey method. Introduction to Verilog
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• carry lookahead adder
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• Classical vs Quantum Computing
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• CMOS INVERTER
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• Comparator
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• Components Of Digital System
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• Conclusion
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• Contents BCD
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• CONTENTS PAGE
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• CONVERSION
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• Counters.
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• d flip flop asynchronous
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• D FLIP FLOP TO JK FLIP FLOP
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• D FLIP FLOP TO SR FLIP FLOP
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• D FLIP FLOP TO T FLIP FLOP
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• Decimal Number System
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• Difference between Mealy Model and Moore Model
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• Edge Triggered D Flipflop
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• Edge triggering
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• Example for time borrowing property
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• Excitation Table
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• Excitation Table and Characteristic Table
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• Finite state machine, state graphs and tables
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• Flif Flop with Synchronous RESET
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• FlipFlop
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• Floating Point Numbers
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• FPFA
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• FPGA
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• FPGA,VLSI design flow using HDL and Introduction to behaviour,logic and physical synthesis
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• Full subtractor
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• graphIT
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• Half Subtractor
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• Hexadecimal Number System
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• Implementation
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• Implementation using D flip flop
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• Important terminologies
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• Introduction
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• Introduction behavior, logic and physical synthesis
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• Introduction of Digital System
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• Introduction to Behavioral modelling
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• Introduction to Number system
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• Introduction to Verilog
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• JK flip flop to D flip flop
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• JK flip flop to SR flip flop
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• JK flip flop to T flip flop
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• JK flipflop with asynchronous input
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• K Map
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• Latches
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• Latches with Asynchronous Enable
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• Latches with Enable
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• Latches with Synchronous Enable
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• Latches without Enable
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• Latches, ffs and Counters
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• Latches,flipflops and counters
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• Laws of Boolean Algebra
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• Logic gates schematic and its MUX representation
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• Main Important Coding Styles of Verilog
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• Master Slave Flipflop
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• Mealy Model
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• Moore Model
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• Moore over lapping Method
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• MSI Logic: Multiplexer, encoder, decoder
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• Multiplier
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• n bit parallel adder
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• NAND and NOR are only universal gates?
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• NON Restoring Division
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• Number representation: BCD, floating point numbers
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• Octal Number System
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• Overlapping Model
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• Parallel adder subtractor
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• Physical synthesis
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• Quine McCluskey Minimization Technique
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• Realization of logic gate using universal gates
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• Register Transfer Level
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• Registers
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• Representing Logic gates using MUX
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• Restoring Division
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• RTL Architecture
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• Rules of Boolean Algebra
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• Sequential Circuit
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• sequential logic like register and introduction to behavioral modelling
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• SET UP AND HOLD TIME
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• Shift register by using other flipflop
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• SISO using T flip flop
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• SR flip flop async
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• SR flip flop to D flip flop
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• SR flip flop to JK flip flop
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• SR flip flop to T flip flop
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• State Diagram and State Table
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• State Reduction
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• State Table and State Diagram
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• Synchronous and Asynchronous Counter
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• Synchronous Counters
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• T FLIP FLOP TO D FLIP FLOP
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• T FLIP FLOP TO JK FLIP FLOP
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• T FLIP FLOP TO SR FLIP FLOP
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• Table
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• To Do : Deterministic Finite State Machines
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• To Do Non Deterministic Finite State Machines
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• To Do: Multiplication Using Adders
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• Tools Used
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• Types of FSM
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• Types of Number System
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• Verilog
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• Verilog code for different adders and subtractors
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• Verilog code for different flipflops
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• Verilog code for different gates
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• Verilog code for different multiplexers
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• VLSI Design Flow using HDL
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• Welcome
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• What is SISO shift register
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• Why NAND gate is preferred?
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