Verilog code for different adders and subtractors - mbits-mirafra/digitalDesignCourse GitHub Wiki

Half adder (Data flow model)

module Half_adder(output SUM, Carry, input A, B);
assign SUM = A ^ B;
assign Carry = A & B;
endmodule

Full adder (Behavioral model)

`timescale 1ns / 1ps
 module full_adder( A, B, Cin, S, Cout);
 input wire A, B, Cin;
 output reg S, Cout;
 always @(A or B or Cin)
 begin
 if(A==0 && B==0 && Cin==0)
 begin
 S=0;
 Cout=0;
 end

 else if(A==0 && B==0 && Cin==1)
 begin
 S=1;
 Cout=0;
 end

 else if(A==0 && B==1 && Cin==0)
 begin
 S=1;
 Cout=0;
 end

 else if(A==0 && B==1 && Cin==1)
 begin
 S=0;
 Cout=1;
 end

 else if(A==1 && B==0 && Cin==0)
 begin
 S=1;
 Cout=0;
 end

 else if(A==1 && B==0 && Cin==1)
 begin
 S=0;
 Cout=1;
 end

 else if(A==1 && B==1 && Cin==0)
 begin
 S=0;
 Cout=1;
 end

 else if(A==1 && B==1 && Cin==1)
 begin
 S=1;
 Cout=1;
 end

 end

 endmodule

Half subtractor (Data flow model)

 module Half_Subtractor(output D, B, input A, B);
 assign D = A ^ B;
 assign B = ~A & B;
 endmodule

Full subtractor (Data flow model)

 module Full_Subtractor(output D, B, input A, B, C);
 assign D = A ^ B ^ C;
 assign B = ~A & B | B & C | C & ~A;
 endmodule