Physical synthesis

Physical synthesis is the process of transforming a Register Transfer Level (RTL) design into a physical implementation of that design, which includes details such as placement of logic gates, routing of signals, and optimization of timing constraints.

Physical synthesis tools take the RTL description of the design and use algorithms to perform various tasks such as technology mapping, placement and routing, timing optimization, power optimization, and more.

Tools are used to ensure that the design meets the desired performance goals such as area and power consumption.

When is physical synthesis used?

Physical synthesis is required when designing complex digital circuits with high-performance requirements. It is particularly useful for designs that are timing-critical, power-sensitive, and require small area utilization. Examples include microprocessors, digital signal processors, ASICs, and FPGAs. Physical synthesis ensures that the logical design is mapped to an optimized physical implementation that meets the design goals and constraints.

The physical synthesis process includes the following steps:

Partitioning

Partitioning is an important step in physical synthesis, which involves dividing the design into smaller, manageable pieces or partitions normally called macros. The goal of partitioning is to simplify the physical implementation process, reduce the overall design complexity, and improve the quality of results.

The partitioning process is typically automated using physical synthesis tools, which use algorithms to analyze the design and determine the best partitioning strategy based on various factors such as the size of the design, timing constraints, and physical layout.

Floor Planning and Placement

Once the design has been partitioned into macros (like rooms in our house), the next step is to place these macros in an optimized way. Just as we would like to have some kind of flow in our living rooms, the goal is to place structure with connections close together .

Floor planning can be done manually or with the help of automated tools. Automated floor planning tools use algorithms to optimize the placement of the functional blocks and reduce the overall chip size.

Placement is the process of determining the physical location of each functional block on the chip. The goal of placement is to minimize the overall wire length and optimize the timing and power requirements of the design.

Clock tree synthesis

Clock tree synthesis (CTS) is a crucial step in the physical design flow of digital integrated circuits (ICs), where a clock distribution network or tree is constructed to ensure that the clock signal is distributed uniformly and with minimum skew to all the sequential elements (such as flip-flops) in the design.

In CTS, the clock signal is first buffered to drive the clock tree, which typically consists of a hierarchy of buffers, inverters, and wires that fan out to the sequential elements.

Once the clock tree is synthesized, it is verified using timing analysis to ensure that the setup and hold times of the sequential elements are met. Any timing violations are fixed by adjusting the clock tree or the placement of the sequential elements.

Routing

Once all the floorplan is completed and placement of the cells is finished on the silicon area, we have to interconnect all the pins (inputs/outputs of the macros) according to the specifications. This process is called Routing.

The routing process involves determining the optimal path for each signal or net, taking into account various factors such as timing constraints, signal integrity, and power consumption. routing is a critical step in the physical design process of an integrated circuit. By optimizing the routing of the design, designers can ensure that the final chip meets the performance, power, and area requirements of the target application.

Timing closure

• Timing closure is the process of ensuring that the timing requirements of a digital design in Verilog are met.
• Timing closure is a critical step in the physical design flow of digital integrated circuits, where the Verilog design is synthesized, placed and routed to meet the timing requirements.
• Timing analysis involves simulating the design using accurate delay models to determine the critical path, which is the path that takes the longest time to propagate through the design.

Physical verification

Physical verification is a critical step in the design flow of digital integrated circuits, including Verilog designs. The purpose of physical verification is to ensure that the Verilog design can be fabricated as a physical chip without any manufacturing issues.

There are several techniques and tools available for physical verification in Verilog, including:

1. Design rule checking (DRC): DRC tools check the Verilog design against a set of design rules, which are specified by the semiconductor foundry. The design rules specify the minimum feature sizes, spacing, and other physical constraints that the design must satisfy. DRC tools can help to identify potential design rule violations, such as short or open circuits.

2. Layout vs. schematic (LVS) verification: LVS tools compare the Verilog netlist with the physical layout to ensure that they match. LVS can help to identify potential errors, such as missing or extra connections between the Verilog netlist and the physical layout.

3. Electrical rule checking (ERC): ERC tools check the Verilog design against a set of electrical rules, which are specified by the semiconductor foundry. The electrical rules specify the maximum current density, voltage drop, and other electrical constraints that the design must satisfy. ERC can help to identify potential electrical violations, such as excessive current density or voltage drop.

Advantages

• It automates the process of converting RTL code to a physical implementation, reducing the time and effort required to design a chip.
• It helps to optimize the design for power, performance, and area.
• It can perform complex optimizations such as clock tree synthesis, routing, and placement, which can be difficult to perform manually.
• It can help identify and correct design issues early in the design process, reducing the risk of errors in the final chip.

Disadvantages

• It can be complex and requires a high level of expertise to use effectively.
• It can produce unexpected results if the input RTL code is not well-written or is incomplete.
• It can be expensive, as it requires specialized software and hardware.
• It can take a significant amount of time to generate a physical implementation, particularly for large and complex designs.