Verilog code for different gates - mbits-mirafra/digitalDesignCourse GitHub Wiki

NOT gate

Untitled Diagram

module NOT_GATE(output Y, input A);
not (Y, A);
endmodule

AND gate

and

module AND_GATE(output Y, input A, B);
and(Y, A, B); 
endmodule

OR gate

module OR_GATE(output Y, input A, B);
or(Y, A, B); 
endmodule

NAND gate

module NAND_GATE(output Y, input A, B);
wire Z;
and(Z, A, B);
not(Y, Z);
endmodule

NOR gate

module NOR_GATE(output Y, input A, B);
nor(Y, A, B); 
endmodule

XOR gate

module XOR_GATE(output Y, input A, B);
xor (Y, A, B); 
endmodule

XNOR gate

module XNOR_GATE(output Y, input A, B);
xnor(Y, A, B);
endmodule