JK flipflop with asynchronous input - mbits-mirafra/digitalDesignCourse GitHub Wiki

The JK Flip-Flop is a sequential device with 3 inputs (J, K, CLK (clock signal)) and 2 outputs (Q and Q’). J and K are control inputs.

PR and CLR are asynchronous inputs - that is the output responds to these input immediately. They are active low inputs.

PR presets the output to 1 and CLR clears the output to 0.
Both PR and CLR cannot be low at the same time - the output is undefined.

Circuit diagram:

Truth table:

From the previous truth table it can be seen that the CLEAR (CLR) and PRESET inputs are active at a low logic level and put on the Q output of the Flip-Flop, a high logic level regardless of the state of the clock and / or the state of the J and K inputs. (see the J, K and clock inputs with an “X”).

In order for the J and K inputs and the clock to be functional, the CLEAR and PRESET inputs must be at a “High” logic level (not active), then:

If inputs are: J = 0 and K = 0, there is a memory or retention state (it keeps the output it had before the entries had changed). (Memory no change)

If inputs are: J = 0 and K = 1, Q is set to “0” and Q’ to a “1” (Reset)

If inputs are: J = 1 and K = 0, Q is set to “1” and Q’ to “0”. (Set)

If inputs are: J = 1 and K = 1, the outputs Q and Q’ of the flip-flop change from a logical level to the opposite (“0” to “1” or “1” to “0”). (Toggle)

The above has effect only when the clock pulse is on the falling edge (see the arrow in the “Clock” column)

Applications 2-bit Up / Down Ripple Counter By connecting the CLK input of the second JK flip flop to Q of the first JK FF, we obtain a 2 bit Up Counter. The output is at both Q of the flip flops. The count sequence for Q1Q0 is 00,01,10,11,00,01 ... where Q1 is the MSB (Most Significant Bit) and Q0 (Least Significant Bit) is the LSB.

Up Down Counter using JK Flip Flops On the other hand, connecting CLK to Q, we obtain a 2 bit Down Counter. The count sequence for Q1Q0 is 00,11,10,01,00,11 ...

When J and K are connected to 1, the JK flip flop is in the toggle mode. By applying low and then high to CLR clears the Q0 and Q1 outputs to 0. By cascading n flip flops, we get a count to 2n counter.

Truncated Ripple Counter The natural count sequence is to run through all possible combinations of the bit patterns before repeating itself. A Truncated Ripple Counter uses external logic to cause the counter to terminate at a specific count. A decade counter counts from 0 to 9.

Working:

TIMING DIAGRAM: