Edge triggered Flip Flop

Different circuit to convert normal clock pulse into an edge-triggered signal

Delay circuit

Implementing edge triggering using semiconductor components is actually quite easy, as it exploits the inherent time delay within every logic gate (known as propagation delay). What we do is take an input signal and split it up two ways, then place a gate or a series of gates in one of those signal paths just to delay it a bit, then have both the original signal and its delayed counterpart enter into a two-input gate that outputs a high signal for the brief moment of time that the delayed signal has not yet caught up to the low-to-high change in the non-delayed signal. An example circuit for producing a clock pulse on a low-to-high input signal transition is shown here:

This circuit may be converted into a negative-edge pulse detector circuit with only a change of the final gate from AND to NOR:

RC differentiator circuit

Above figure shows the RC differentiator circuit which is normally designed to generate clock input for D flip-flop. In the RC differentiator circuit, RC time constant is made much smaller than the clock pulse width. Because of very small time constant the capacitor charges immediately when the clock goes high. This exponential charging of capacitor produces a narrow positive spike across the resistor. Similarly capacitor discharges fully at the trailing edge of the clock pulse resulting in narrow negative spike.

The narrow positive spike activates the AND gates A1 and A2 for an instant and samples the value of D input at that instant. It can be seen from the above figure that exactly when positive spike hit the AND gates, D and its compliment hit the flip-flop. The flip-flop will SET and RESET as the value of D is at logic 1 or logic 0 respectively. When the negative spike hit the flip-flop then both the AND gates are disabled and the output of both A1 and A2 are at logic 0. Since both S and R input are at logic 0 so output will retain the last state and observes no change. It can be observed from the truth table that during negative spike of clock signal the D input has no significance and the output becomes independent of the value of D input. This mode of operation is termed as edge triggering because the flip-flop responds only when the clock is in transition between the two voltage states.

Master slave flip flop

• Another way to produce edge triggered function is by connecting two level triggered laches back to back
• A master-slave flip-flop is normally constructed from two laches: one is the Master latch and the other is the Slave.
• In addition to these two laches, the circuit also includes an inverter.
• The inverter is connected to clock pulse in such a way that the inverted CP is given to the slave latch.

Master slave SR flip flop

A master-slave SR flip-flop is a type of flip-flop circuit that uses two gated SR latches to store a single bit of information. The two latches are connected in a "master-slave" configuration, with the output of the master latch feeding into the input of the slave latch. This configuration allows the flip-flop to be edge-triggered, with changes in the input signal only affecting the output on the rising edge or falling edge of the clock signal.

Working:

When the clock signal is high master is active and slave is inactive, master will take the input and provide it to slave but slave will hold the previous state, when the clock signal is low master is inactive slave will be active. Slave will produce output based on output provided by master in previous state.

If the set input (S) is high and the reset input (R) is low when the clock signal goes high, the master latch sets its output to high (Q=1) and the slave latch follows suit. Conversely, if the reset input (R) is high and the set input (S) is low, the master latch resets its output to low (Q=0) and the slave latch follows suit.

If both the set and reset inputs are high when the clock signal goes high, the outputs of the master and slave latches are undefined, and the flip-flop may enter a metastable state, which can cause unpredictable behavior. To prevent this, the set and reset inputs should not both be high at the same time.

Timing diagram:

Master latch operation: When the clock signal is high, the master latch is enabled, and it captures the input signals (S and R). If the input signals cause the master latch to change state (i.e., S=1 and R=0, or S=0 and R=1), the output of the master latch changes accordingly. If the input signals do not cause the master latch to change state (i.e., S=0 and R=0, or S=1 and R=1), the output of the master latch remains unchanged.

Slave latch operation: When the clock signal is low, the master latch is disabled, and its output is "locked in" to the input of the slave latch. The slave latch is enabled, and it follows the output of the master latch. If the output of the master latch changed during the previous clock cycle (i.e., the clock signal was high), the output of the slave latch will also change to reflect the new state.

This two-step process allows the master-slave SR flip-flop to capture changes in the input signals only on the rising or falling edge of the clock signal, rather than on every clock cycle. This makes the flip-flop more reliable and less prone to glitches and false triggering.

Application:

While there is no application where only a SR master-slave flip-flop can be used, there are certain situations where it may be preferred over other types of master-slave flip-flops, such as the JK and D flip-flops.

One such situation is when you want to store a single bit of information in a circuit and require a simple and straightforward implementation. The SR flip-flop is the most basic type of flip-flop, requiring only two inputs, namely the S (set) and R (reset) inputs, to store a single bit of information. In contrast, the JK and D flip-flops require additional inputs, such as the J and K inputs for the JK flip-flop, and the D input for the D flip-flop.

Another situation where the SR master-slave flip-flop may be preferred is when there is a requirement to clear or reset the stored data. The SR flip-flop has separate set and reset inputs, allowing for more precise control over the stored data. In contrast, the JK and D flip-flops require additional logic to implement clear or reset functionality.

Master slave D flip flop:

A negative-edge triggered D type master/slave flip-flop consists of a pair of D-latches connected, as shown in Figure. The master follows the D input while the clock is high, and latches the value of the input at the output of the master on the trailing edge of the clock pulse. The master is now disabled and will remain so until the clock goes high again. When the clock goes low the inverted clock signal at the clock input of the slave enables it, and the output of the master is transferred to the output of the slave. When the clock next goes high the slave is disabled and will remain so until the clock goes low again. Edge-triggering is indicated on the symbolic diagram by the triangle at the clock input. This triangle is termed a dynamic input indicator.

Working:

• When the clock signal goes high, the master latch is enabled, and the data input (D) is transferred to the master latch's output (Q).
• At the same time, the slave latch is disabled, so the output of the master latch is not passed through to the output of the slave latch yet.
• When the clock signal goes low, the master latch is disabled, and the output of the master latch is latched into the slave latch.
• At the same time, the slave latch is enabled, so the output of the master latch is passed through to the output of the slave latch.
• The output of the master-slave D flip-flop remains stable until the next clock edge, at which point the process repeats.

The circuit can be modified to provide leading-edge triggering by including a second inverter in the clock line.

Master slave T flip flop:

• A Master-Slave T flip-flop is a type of digital circuit that is used for storing or toggling the binary data . It consists of two T latch connected together in a way that allows them to operate as a single unit called Master-Slave Flipflop. So, in a Master-Slave flip-flop, the slave is designed to obey or follow the master latch.

• The "master" latch is controlled by an input signal called the "clock," and it sets or resets the output based on the state of the input signal. The "slave" latch is connected to the output of the master latch and also controlled by the clock signal. It captures and holds the value of the master's output when the clock signal transitions from one state to another
• When the clock pulse goes to 1, the slave is isolated; T inputs may affect the state of the system. The slave latch is isolated until the CP goes to 0. When the Clock pulse goes back to 0, information is passed from the master latch to the slave and output is obtained.

• When T = 0 and clk is 1, master will be active and slave wont be active due to a inverter. Lets assume a value 0 to Q ad Q' will be 1 to both master and slave output hence there will be no change in the output and occurs in positive edge for master and when clock is 0 it occurs in negative edge for slave and it remains in the hold state.
• When T = 1, and clk is 1, master will be active and slave wont be active due to a inverter. Lets assume a value 0 to Q ad Q' will be 1 to both master and slave output hence output Q will be 1 and Q' is 0 and then at the positive edge of the clock pulse, the master flip flop toggles (means the change of the previous state into its opposite state), and at the negative edge of the clock pulse, the slave flip flop toggles.

Applications of Master-Slave T-flipflops

• The main application of master slave T-flip flop is it is used as an Frequency divider.

Frequency divider

• A normal T- flipflop will act as mod 2 frequency divider as you can see in the diagram below.
• If we consider a pos edge clock, Qs is the output of the first T-ff and Qe is the output of second T-ff.

• Eight comlplete cycle of clock gives Four complete cycle of Qs ,this output is from the first T-ff and it is acting as an mod-2 divider.
• To make act as an mod 4 divider we need to connect the output Qs as an pos edge clock to the second T-ff.
• Eight comlplete cycle of clock gives two complete cycle of Qe and it is acting as an mod-4 divider. *We can design mod-8 or mod-16 by adding more T-flip flops.

Master-Slave JK Flipflop

Race Around Condition

A race-around condition is a type of timing problem that can occur in a JK flip-flop when the inputs change too quickly, caused by the output when it oscillates rapidly between two states. This condition can occur when the J and K inputs of the flip-flop are both high, causing the output to toggle rapidly between 1 and 0. This may result in the flipflop being unstable or uncertain.

Why Master-Slave Flipflops?

Master-Slave flipflops are mainly used to avoid the timing problems associated with JK flip-flops, such as the possibility of race conditions that can occur when both inputs change simultaneously.

When the clock signal transitions from low to high, the master latch that latches the input data and sets its output, while the slave latch remains in its previous state. Then, when the clock signal transitions from high to low, the slave latch captures the output of the master latch, and its output updates to the same state as the master latch.

By using this master-slave arrangement, the flip-flop avoids race conditions and provides a more reliable and predictable behavior than simple latches or flip-flops.

Master-slave JK flipflop

A Master-Slave JK flip-flop is a type of digital circuit that is used for storing binary data. It consists of two JK latch connected together in a way that allows them to operate as a single unit called Master-Slave Flipflop. So, in a Master-Slave flip-flop, the slave is designed to obey or follow the master latch.

The "master" latch is controlled by an input signal called the "clock," and it sets or resets the output based on the state of the input signal. The "slave" latch is connected to the output of the master latch and also controlled by the clock signal. It captures and holds the value of the master's output when the clock signal transitions from one state to another.

Working

• When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the system. The slave latch is isolated until the CP goes to 0. When the CP goes back to 0, information is passed from the master latch to the slave and output is obtained.

• When J = 0, K = 0 and clk is 1 master will be active and slave wont be active due to a inverter. Lets assume a value 0 to Q ad Q' will be 1 to both master and slave output hence there will be no change in the output and occurs in positive edge for master and when clock is 0 it occurs in negative edge for slave and it remains in the hold state.

• When J = 0, K = 1 and clk is 1 master will be active and slave wont be active due to a inverter. Lets assume a value 0 to Q ad Q' will be 1 to both master and slave output hence output remains same as input and occurs in positive edge for master and when clock is 0 it occurs in negative edge for slave and it remains in the reset state.

• When J = 1, K = 0 and clk is 1 master will be active and slave wont be active due to a inverter. Lets assume a value 0 to Q ad Q' will be 1 to both master and slave output hence output remains same as input and occurs in positive edge for master and when clock is 0 it occurs in negative edge for slave and it remains in the set state.

• When J = K = 1, and clk is 1 master will be active and slave wont be active due to a inverter. Lets assume a value 0 to Q ad Q' will be 1 to both master and slave output hence output Q will be 1 and Q' is 0 and then at the positive edge of the clock pulse, the master flip flop toggles (means the change of the previous state into its opposite state), and at the negative edge of the clock pulse, the slave flip flop toggles.

Applications of Master-Slave flipflops

1. Counters :

Counters are used in many electronic devices, including digital clocks, timers, and frequency dividers. In these devices, Master-Slave JK flip-flops are used to store and update the count value.

2. Memory Chips :

Memory chips are used to store binary data for a short period. RAM (Random Access Memory) chips use Master-Slave JK flip-flops to store and retrieve data.

3. Digital Signal Processors (DSPs):

DSPs are used to process digital signals in real-time. In these devices, Master-Slave JK flip-flops are used in the pipelining and sequencing of digital signal processing operations.

Advantages :

1. Elimination of race conditions: The master-slave JK flip-flop eliminates race conditions that can occur in other types of flip-flops.

2. Improved Noise Immunity : The Master latch captures the input signal and holds it for a short period of time before it is transferred to the Slave latch. During this time, any noise on the input signal is filtered out, and only a clean signal is transferred to the Slave latch.

Disadvantages :

1. Complexity: The master-slave JK flip-flop requires more circuitry than other types of flip-flops, such as the D flip-flop. This complexity makes it more difficult to design and test.

2. Power Consumption: The master-slave JK flip-flop requires more power to operate than other flip-flops. This can be an issue in battery-powered or low-power applications where power consumption is a concern.