FPGA,VLSI design flow using HDL and Introduction to behaviour,logic and physical synthesis - mbits-mirafra/digitalDesignCourse GitHub Wiki
| Sr.no | TOPICS |
|---|---|
| 1 | FPGA |
| 2 | VLSI design flow using HDL |
| 3 | Introduction to behaviour,logic and physical synthesis |
| Sr.no | TOPICS |
|---|---|
| 1 | FPGA |
| 2 | VLSI design flow using HDL |
| 3 | Introduction to behaviour,logic and physical synthesis |