The Mealy model is a type of finite state machine used in digital electronics and computer science. It is named after its creator, George H. Mealy.

In the Mealy model, the outputs of the machine are a function of both its current state and its inputs. This means that the machine can have different outputs for the same input, depending on its current state.

Q= Present state of the circuit

Q⁺=Next state of the circuit

X=Present input

Y=Outputs

The next state is a Boolean function of the present inputs and the present state

Q⁺=f₁(X,Q)

The outputs are also the functions of present inputs and present state

Y=f₂(X,Q)

Design a synchronous circuit using positive edge JK flip flop with minimal combinational gating to generate the following sequence 0-1-2-0 if input X=0 and 0-2-1-0 if input X=1. Provide an output which goes to high to indicate the non zero states in the 0-1-2-0 sequence. Is this a Mealy machine?

There are 3 states:

• 0-00

• 1-01

• 2-10

Since there r only 3 states the 4th state 11 is represented with -

Excitation Table with Flip flop inputs

The Karnaugh maps for simplifying flip-flop inputs and the output are shown below

• Kmap for JB

J_B=X^|Q_A+XQ^|_A

J_B=X^Q_A

• Kmap for KB

K_B=1

• Kmap for JA

J_A=X^'Q_B^' + XQ_B

J_A=(X^Q_B)^'

• Kmap for KA

K_A=1

• Kmap for Y

Y=X^|Q_B+X^|Q_A

Step 5: Design the Circuit

Here,

Q={A,B} , Q⁺={A⁺,B⁺}

Q⁺=f₁(X,Q) = f₁(X,A,B)

Y=f₂(X,Q)=f₂(X,A,B) = X^|(A+B)

Observe that both the next state and the output are Boolean functions of the input and the present state.

Therefore the given synchronous circuit is a Mealy machine.

Implementation using D flip flop

State Reduction

Overlapping Model