SR flip flop async - mbits-mirafra/digitalDesignCourse GitHub Wiki

The SR Flip-Flop is a sequential device with 3 inputs (S, R, CLK (clock signal)) and 2 outputs (Q and Q’). S and R are control inputs.

PR and CLR or SET and RST are asynchronous inputs - that is the output responds to these input immediately. They are active low inputs.

SET sets the output to 1 and RST resets the output to 0.
Both SET and RST cannot be low at the same time - the output is undefined.

Circuit diagram:

Truth table:

TIMING DIAGRAM: