RTL Architecture

Register Transfer Level (RTL) architecture is a hardware design methodology used to describe the behavior of digital circuits in terms of data flow between registers, memory units, and arithmetic and logic units (ALUs). It involves defining the functions performed by a digital system in terms of the operations performed on registers and data transfers between them.

Inputs are read from a register. There could be a sequence of combinational design, The data is given to the combinational logic to perform specific function then the output is once again transferred to a register, the whole combinational unit must perform one particular operations within one clock period so that output can be delivered to register within a clock cycle. The combinational unit may perform multiple such operation over different clock cycle. Therefore there must be a state machine which is trying to manage operations and decides which operations to perform in which clock cycle. These state machines will consists of state registers. These state machines will determine what is the current state and what will be the next state, based on this it will control the combinational logic to perform particular function.

In Register Transfer Level (RTL) architecture, the data path and control path are two crucial components that work together to implement the desired digital system.

Data Path: The data path in RTL architecture is responsible for the movement and processing of data. It consists of various functional units such as registers, arithmetic and logic units (ALUs), multiplexers, demultiplexers, and memory units. These functional units are interconnected with buses to enable the transfer of data between them.

Control Path: The control path in RTL architecture is responsible for the overall operation of the digital system. It generates control signals that determine the behavior of the data path. The control path receives inputs from the external environment, interprets these inputs, and generates the appropriate control signals to coordinate the actions of the functional units in the data path.

Latency and Throughput

• Latency can be defined as the delay between the time input is read and the time output corresponding to it is produced. Latency can be introduced by various factors such as the processing time of the system, the time required to fetch data from memory, and the time required to perform operations such as arithmetic or logical operations.
• Throughput can be defined as the rate at which input can be read and processed. throughput is often limited by the speed of the processing elements, the data transfer mechanism, and the memory access speed.

In the first example both throughput and latency are 2ns, since the delay of entire circuit is 2ns and also next in put a can be applied after 2ns. In the second example D flip flop is introduced within the circuit. Assuming it is the ideal flip flop with 0 delay, the entire circuit delay remains the same but rate at which input can be applied is increased, since D flip flop can store data after 1ns next input can be applied after 1ns instead of 2ns hence the throughput is reduced from 2ns to 1ns.

RTL Structural and Datapath

In the first step i.e., at S0 state it will read the data

At S1 state, contents of R1 and R2 are added to register R5

At S2 state, contents of R5 and R3 are added and stored back to register R5

At S3 state, contents of R5 and R4 are added and stored into register R5

Then again register R5 is fed back to S0 state and then in this state, it will again freshly read the data and continues the process.

As you can see, S0 state reads the data at the first clock cycle, then in the second clock cycle S1 state operation takes, later in the 3rd and 4th clock cycle S2 and S3 state operation takes place respectively.

The controller will decide which select line to use.

Load signal(LD) is enable signal which is given to register, when LD is on then the register works.

At S0 state, all LD(load signal) is enabled except LD5, and the select signal doesn't matter.

At S1 state, all 4 LD signals are zero, then LD5 is set and select S0 is enabled.

At S2 state, LD5 and S2 are enabled.

At S3 state, LD5 AND S1 are enabled.