Verilog code for different multiplexers - mbits-mirafra/digitalDesignCourse GitHub Wiki

2:1 multiplexer (Data flow model)

module m2_1(I0, I1, S, Y);
output Y;
input I0, I1, S;
assign Y=(S)?I1:I0;
endmodule

4:1 multiplexer (Data flow model)

module m4_1 ( input I0,input I1, input I2, input I3, input S0, S1,output Y); 
assign Y = S1 ? (S0 ? I3 : I2) : (S0 ? I1 : I0); 
endmodule

8:1 multiplexer (Data flow model)

module m8_1(output Y, input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2);
assign S1bar=~S1;
assign S0bar=~S0;
assign S2bar=~S2;
assign Y = (D0 & S2bar & S1bar & S0bar) | (D1 & S2 & S1bar & S0bar) | (D2 & S2bar & S1 & S0bar) | (D3 & S2 & S1 & S0bar) | (D4 & S2bar & S1bar & S0) | (D5 & S2 & S1bar & S0) | (D6 & S2bar & S1 & S0) | (D7 & S2 & S1 & S0);
endmodule