Page Index - thepinkmile/Enigma-NG GitHub Wiki
407 page(s) in this GitHub Wiki:
- Home
- Enigma NG: Digital Cryptography Ecosystem
- 🚀 Project Vision
- Tools Used
- Core Component Overview
- Core Requirements
- Board Status Snapshot
- 🗺️ System Architecture
- 🔌 Hardware Architecture
- 1. Power Module (The Heart)
- 2. Controller Board (The Brain)
- 3. JTAG Module
- 4. Actuation Module (AM)
- 5. Stator Board (Nervous System)
- 6. Encoder Module (Universal Interface)
- 7. Settings Board (Configuration Panel)
- 8. Rotor Module (The Engine)
- 9. Extension Board
- 10. Reflector Board
- 💻 Software Implementation
- 1. Linux Kernel Driver
- 2. .NET 10 GUI (The Terminal)
- 3. VHDL Firmware (The Navigators)
- ⚠️ Safety & Design Rules (KiCAD 9)
- 📅 Development Roadmap
- Contributions
- Licensing
- Design Log DEC 001 3v3 enig used throughout 3v3 system removed from btb interconnect
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- Design Log DEC 002 poe option a2 selected coilcraft poe600f 12ld
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- Design Log DEC 003 poe output 12v or ing priority logic required
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- Design Log DEC 004 supercap charge current 05a under poe
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- Design Log DEC 005 tps25980 efuse replaces tps259474l
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- Design Log DEC 006 stusb4500 negotiates 15v5a 75w
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- Design Log DEC 007 dual interleaved lmq61460 q1 5v buck 12a
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- Design Log DEC 008 tps25750 emulates 5v5a pd profile to cm5
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- Design Log DEC 009 legacy controller probe access pin 14 reassigned to sw led ctrl
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- Design Log DEC 010 inc 14 deferred legacy probe access esd protection post prototype
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- Design Log DEC 011 all power rails on power module 3v3 enig serves rotor stack
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- Design Log DEC 012 u4 tps25750 replaced with tps25751drefr nrnd resolution
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- Design Log DEC 013 l3 emi inductor changed to bourns srp1265a 100m
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- Design Log DEC 014 controller board uses erf8 female on both btb connectors for blind mate assembly
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- Design Log DEC 015 link beta connector reduced from 80 pin to 40 pin erf8 020 erm8 020
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- Design Log DEC 016 jtag controlled impedance and series termination
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- Design Log DEC 017 minimum 4 layer stackup for all non controller boards
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- Design Log DEC 018 connector pinout ownership model
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- Design Log DEC 019 poe transformer topology acf option a selected
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- Design Log DEC 020 gnd chassis rib clearway enig bond
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- Design Log DEC 021 supercapacitor bank upgrade 2x2 2s2p 2x3 2s3p
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- Design Log DEC 022 jdb ft232h clock source dedicated 12mhz smd crystal selected
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- Design Log DEC 023 jdb gnd chassis omitted mounting holes tied to gnd
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- Design Log DEC 024 jdb is complete jtag master controller jtag lines are pass through
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- Design Log DEC 025 cm5 shutdown mechanism hardware driven ltc3350 software support deferred
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- Design Log DEC 026 rotor position encoder as5600 replaced with single track capacitive encoder
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- Design Log DEC 027 rotor position readback via jtag virtual jtag user0 udr
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- Design Log DEC 028 split dual board rotor architecture
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- Design Log DEC 029 supercapacitor hold up specification 25f abracon cells 2s4p 20 s at 15w
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- Design Log DEC 030 5v main backup switchover transient fix r14 r30 c35
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- Design Log DEC 031 cm5 virtual keyboard key injection feature architecture
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- Design Log DEC 032 settings board panel mount configuration controls with cm5 override
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- Design Log DEC 033 dsi1 display connector provision for optional lid touchscreen
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- Design Log DEC 034 switch hardware refresh settings board toggle discrete rgb led ruggedized pm sw1
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- Design Log DEC 035 hid keyboard and lightboard use a 40 position qwerty derived layout for the 64 character code space
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- Design Log DEC 036 link beta former monitor pins reallocated as grouped power rails
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- Design Log DEC 037 link beta pin map regrouped around dedicated jtag and i2c guard bands
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- Design Log DEC 038 controller centric dock architecture replaces legacy link alpha link beta backplane
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- Design Log DEC 039 enclosure connected boards use gnd chassis daughterboards are exempt
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- Design Log DEC 040 diagnostics banks removed from active design specs pending coupon review
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- Design Log DEC 041 encoder modules use epm570 with digital debounce and role by programming
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- Design Log DEC 042 encoder port pin 8 carries hid local enc active n
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- Design Log DEC 043 shared actuation module replaces direct controller servo gpio
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- Design Log DEC 044 fdc2114 internal oscillator selected clkin gnd
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- Design Log DEC 045 rotor samtec erm8erf8 connectors require esd protection
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- Design Log DEC 046 bypassdecoupling capacitor voltage rating 50v retained on all non pm boards
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- Design Log DEC 047 or ing mosfet corrected to csd17578q5a
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- Design Log DEC 048 esd protection extended to host side rotor facing btb connectors
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- Design Log DEC 049 rotor internal headers renamed to j convention connector count updated to 8 bom unified
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- Design Log DEC 050 encoder blade terminal refdes corrected from bt to j convention
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- Design Log DEC 051 settings board renamed to user settings module board code sbd usm
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- Design Log DEC 052 variant specific fdc2114 refdes use ab suffix convention
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- Design Log DEC 053 extension port connector upgraded from bhr 20 vua 20 pin to 2bhr 30 vua 30 pin
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- Design Log DEC 054 signal net renamed pwr but pwr but n active low suffix conformance
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- Design Log DEC 055 f 108 system wide reference designator and requirement id consecutive renumbering
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- Design Log DEC 056 relocate investigation documents to board owned folders
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- Design Log DEC 057 daughterboard mounting hole specification and standoff bom ownership
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- Design Log DEC 058 jdb connector upgrade hat headers to df40c 20 btb
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- Design Log DEC 059 erm8erf8 stacking height confirmed rotor stack assembly specification created
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- Design Log DEC 060 jtag daughterboard renamed to jtag module jdb prefix replaced with jm
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- Design Log DEC 061 pass 7 review corrections ctlstarotencamgrsstatus updates
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- Design Log DEC 062 ctl poe t1 selection tdk b82806d0060a120 topology acf flyback acf forward
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- Design Log DEC 063 ctl poe l1 selection yageo pa4343333nlt acf forward output inductor
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- Design Log DEC 064 ctl poe c17 final part selection kemet c0805c223k2racauto 22nf 200v x7r 0805
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- Design Log DEC 065 system wide stackup code correction and jlcpcb authoritative impedance values
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- Design Log DEC 066 grs canonical pcb stackup authority consolidation
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- Design Log DEC 067 am sw1sw2 tactile switch rating accepted for production
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- Design Log DEC 068 pm per input bulk capacitors and output source quality bulk banks
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- Design Log DEC 069 pm per input polyfuse protection and uvlo resistor recalculation
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- Design Log DEC 070 mcp23017 i²c silicon restriction gpb7gpa7 review and cfg apply n reassignment
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- Design Log DEC 071 usm spdt switch dual terminated wiring and pull down resistor removal
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- Design Log DEC 072 review pass 9 findings and resolutions
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- Design Log DEC 073 ltc3350 rt resistor correction 332 kω 133 kω amends dec 030
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- Design Log DEC 074 rename cpld reset signal sys reset n cpld reset n
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- Design Log DEC 075 tps25751 option c external eeprom isolated i2ct debug header on power module
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- Design Log DEC 076 pm 3v3 architecture redesign 3v3 main3v3 enig rail split j4 dual purpose programming j6 removal and q12 parallel p fet selection
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- Design Log DEC 077 retrospective rotor ttd daisy chain no series termination resistors amends dec 016
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- Design Log DEC 078 cpld reset n stator buffer bss138 n channel mosfet new decision references dec 077
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- Design Log DEC 079 c20 voltage rating correction 25v 35v amends dec 072 bom item 1
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- Design Log DEC 080 retrospective pm and stator dock connector redesignation amends dec 038
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- Design Log DEC 081 retrospective rotor ttd no series resistor policy in addition to dec 016
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- Design Log DEC 082 10µf bulk reservoir capacitor upgrade 25v 0805 50v 1206 all boards
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- Design Log DEC 083 retire all boards bomjson consolidate bom authority in design spec files and consolidated bom
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- Design Log DEC 084 cypher stack architecture migration and board role consolidation
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- Design Log DEC 085 stack output j4 power pin zero ohm links prototype test
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- Design Log DEC 086 cypher input common variant restructure 10 numeric variant single i2c address
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- Design Log DEC 087 cypher input led colour architecture moved off plain bits onto local rgb select circuit
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- Design Log DEC 088 plugboard jacks wired directly to cypher board spade bank j4j6 reserves 5v main
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- Design Log DEC 089 board role id widened to 4 bit capability bitmask cpld pin freeing and j5 migration
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- Design Log DEC 090 cypher board j3 stack input side full 50 pin allocation and actuate request in out n signal pair
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- Design Log DEC 091 j3 esd protection extended to actuate request pins and actuation gating resolved to cypher cpld
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- Design Log DEC 092 cypher board j4 stack output side full 50 pin allocation
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- Design Log DEC 093 actuate request end to end signal path j4 rename rotor interposer connectors extended
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- Design Log DEC 094 connector ownership reassignment for reused chain templates
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- Design Log DEC 095 actuate request esd protection completed stack output passive wiring defined
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- Design Log DEC 096 stack blanking board corrected actuate request bridging added
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- Design Log DEC 097 cypher j3 actuate request out n wired as round trip verification input
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- Design Log DEC 098 controller cypher dock split power molex signal samtec amends dec 038 dec 080
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- Design Log DEC 099 cm5 i2c bank architecture mipi0 to mipi1 swap pwm gpclk reservation
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- Design Log DEC 100 jtag module actuation module retirement from controller board
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- Design Log DEC 101 cypher ina219 i2c address aligned to pm default
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- Design Log DEC 102 cypher ft232h 3v3 vregin self powered 5v usb net retired
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- Design Log DEC 103 hid usm hub connector topology rework
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- Design Log DEC 104 user settings module role reworked as hid colour audio hub and jtag i2c spine
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- Design Log DEC 105 cfg route moved to full cm5 software control physical usm switches retired
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- Design Log DEC 106 cypher plugboard reduced to mechanical connector only board
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- Design Log DEC 107 usm hid connector four colour style signal expansion
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- Design Log index
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- Electronics Actuation Module Board Layout
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- Electronics Actuation Module Design Spec
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- Electronics Boards Overview
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- Electronics Consolidated BOM
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- Electronics Controller Board Layout
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- Electronics Controller Design Spec
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- Electronics Controller PoE Power Analysis
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- Electronics Controller PoE Power Analysis Coilcraft v2
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- Electronics Cypher Board Layout
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- Electronics Cypher Design Spec
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- Electronics Cypher Input Board Layout
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- Electronics Cypher Input Cypher Input 10 Numeric Design
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- Electronics Cypher Input Cypher Input 26 Char Design
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- Electronics Cypher Input Cypher Input 64 Char Design
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- Electronics Cypher Input Design Spec
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- Electronics Cypher Input TEMP Key Mapping Review
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- Electronics Cypher Output Board Layout
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- Electronics Cypher Output Cypher Output 10 Numeric Design
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- Electronics Cypher Output Cypher Output 26 Char Design
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- Electronics Cypher Output Cypher Output 64 Char Design
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- Electronics Cypher Output Design Spec
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- Electronics Cypher Plugboard Board Layout
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- Electronics Cypher Plugboard Cypher Plugboard 10 Numeric Design
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- Electronics Cypher Plugboard Cypher Plugboard 26 Char Design
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- Electronics Cypher Plugboard Cypher Plugboard 64 Char Design
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- Electronics Cypher Plugboard Design Spec
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- Electronics Electrical Design
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- Electronics Encoder Module Board Layout
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- Electronics Encoder Module Design Spec
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- Electronics Extension Board Layout
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- Electronics Extension Design Spec
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- Electronics JTAG Module Board Layout
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- Electronics JTAG Module Design Spec
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- Electronics JTAG Module JTAG Integrity
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- Electronics Power Budgets
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- Electronics Power Module Board Layout
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- Electronics Power Module Design Spec
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- Electronics Power Module Millitary Battery Connection Option
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- Electronics Reflector Board Layout
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- Electronics Reflector Design Spec
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- Electronics Rotor Board Layout
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- Electronics Rotor Design Spec
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- Electronics Rotor Rotor 26 Char Design
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- Electronics Rotor Rotor 64 Char Design
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- Electronics Stack Blanking Board Layout
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- Electronics Stack Blanking Design Spec
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- Electronics Stack Input Board Layout
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- Electronics Stack Input Design Spec
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- Electronics Stack Interposer Board Layout
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- Electronics Stack Interposer Design Spec
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- Electronics Stack Output Board Layout
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- Electronics Stack Output Design Spec
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- Electronics Stator Board Layout
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- Electronics Stator Design Spec
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- Electronics System Architecture
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- Electronics User Settings Module Board Layout
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- Electronics User Settings Module Design Spec
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- Guides Classroom Guide
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- Guides Maintenance Guide
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- Guides User Manual
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- Mechanical Complete System Assembly Design Spec
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- Mechanical Extension Design Spec
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- Mechanical Keyboard Assembly Design Spec
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- Mechanical Lightboard Assembly Design Spec
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- Mechanical Main Enclosure Design Spec
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- Mechanical Plugboard Assembly Design Spec
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- Mechanical Power Module Design Spec
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- Mechanical Reflector Design Spec
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- Mechanical Rotor Actuation Assembly Design Spec
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- Mechanical Rotor Design Spec
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- Mechanical Rotor Stack Assembly Design Spec
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- Procedures Lab Tests
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- Procedures PAS PowerModule V1
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- Production JLCPCB Manufacturing
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- Software Actuation Module Design Spec
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- Software CPLD Logic Encoder Logic
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- Software CPLD Logic Rotor Logic
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- Software GUI App Design Spec
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- Software GUI App Wireframes README
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- Software Linux OS Power Management
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- Standards Certification Evidence
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- Standards Global Routing Spec
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