Electronics Power Budgets - thepinkmile/Enigma-NG GitHub Wiki

Enigma-NG Power Budgets

Status: Draft Version: v.0.1.0 Associated Hardware Revision: Rev A Last Updated: 2026-09-11

Design Constraint Hierarchy

  1. TPS75733KTTRG3 LDO (Power Module U7): 3.0A maximum output - hard limit, component not to be changed.
  2. PM dock J1 3V3_ENIG allocation: 2 x 3V3_ENIG contacts at 6A/contact - comfortably above the LDO limit.
  3. Stator dock J5 3V3_ENIG allocation: 4 x 3V3_ENIG large blades plus additional guarded-return capacity - connector is not the bottleneck, the LDO is.
  4. Available to Stator + Rotor stack: LDO output minus Controller-local consumption (CM5 GPIO reference, pull-ups, and local housekeeping) ≈ 2.95A (Controller overhead ≤ 50mA).

3V3_ENIG Load Analysis

Per-Device Current (Intel MAX II EPM570T100I5N [Encoder x6, Rotor x30, Stator x1] @ 3.3V)

Operating condition ICC (core) Source
Static (no switching) ~5 mA Intel MAX II Datasheet ICC_STATIC
Typical cipher logic (50 MHz toggle) ~25 mA Intel MAX II Power Estimator (50% toggle, 50% resource use)
Worst-case (100 MHz, 80% resource use) ~80 mA MAX II Datasheet ICC_DYNAMIC worst case

Design value used: 50 mA per CPLD (conservative typical - accounts for VHDL cipher switching without being an unachievable worst-case peak).

Per-Device Current (TI FDC2114RGHR Capacitive Sensor IC @ 3.3V)

Condition ICC
Active 2.1 mA typ

3V3_ENIG Allocation Table

Consumer Count Per-unit (mA) Total (mA) Notes
Stator CPLD (U1, EPM570T100I5N) 1 50 50 JTAG forwarding + ENC signal routing
HID Encoder CPLDs (EPM570 x2) 2 50 100 Keyboard encode + lightboard decode CPLDs
Plugboard Encoder A CPLDs (EPM570 x2) 2 50 100 Stecker pass A encode/decode pair
Plugboard Encoder B CPLDs (EPM570 x2) 2 50 100 Stecker pass B encode/decode pair
FT232H (Cypher Board USB-JTAG bridge; VREGIN+VCCD+VCCIO+VPLL+VPHY, all 3V3_ENIG) 1 100 100 Self-powered, Rev C silicon, 3.0-3.6V VREGIN; see DEC-102
Rotor CPLDs (EPM570T100I5N x30) 30 50 1500 All rotors cipher-active simultaneously
Rotor FDC2114RGHR capacitive sensor ICs (U2/U3 or U2/U4, 2 ICs per rotor, 60 ICs total) 60 2.1 126 Continuous position polling; two ICs per rotor add 4.2 mA to the 50 mA CPLD budget, giving 54.2 mA typ / 55 mA budget per rotor
INA219 current monitor (Stator) 1 1 1 Negligible
INA219 current monitor (Power Module) 1 1 1 Negligible
Stator GPIO expanders (MCP23017 x3) 3 10 30 U6, U7, U8 on shared I2C-1; monitor / control overhead only
PM-local GPIO expander (PCA9534A x1) 1 5 5 U14 @ 0x3F; PM status + SW1 runtime RGB handoff control
User Settings Module GPIO expanders (MCP23017 x3) 3 25 75 U1, U2, U3 on the shared Stator I2C-1 bus
Extension Buffer ICs (SN74LVC2G125DCUR) 5 2 10 TCK/TMS re-drive for each 5-rotor group; one per Extension board; negligible load
Stack-Input STM32G071K8T3TR MCUs (native Actuation Module, one per mini-stack) 6 5 30 Placeholder conservative estimate (Run mode ~2.9 mA typ @ 24 MHz per local stm32g071.md Table IDD(Run), rounded up for GPIO/peripheral overhead); actual figure TBD once firmware clock configuration and solenoid driver circuit are finalised - see Stack-Input/Design_Spec.md §4
Controller-local housekeeping - - 50 Controller overhead subtracted before Stator distribution
Typical total 2,283 mA
Rounded budget ≤ 2.29 A

Headroom vs LDO Limit

Limit Value Margin
LDO hard limit 3.00 A -
Typical worst-case load 2.29 A +0.71 A (24%)
Controller↔Stator dock capacity Above 3.00 A Not the constraint

✔ Conclusion: The 3A TPS75733KTTRG3 LDO provides ~24% headroom above the full downstream worst-case typical load. No LDO upgrade is required for the current 30-rotor design. Telemetry note: The Stator INA219 / shunt path still measures the rotor-stack distribution branch at about 2.05 A typical. The extra ~230 mA above that figure is the User Settings Module's local logic load, the Stack-Input STM32G071 MCU placeholder, and the FT232H's full 3.3V-VREGIN draw on the shared 3V3_ENIG rail.

3V3_ENIG Conflict Resolution

STA-05 / STA-06: Shunt resistor and power figure reconciliation

Document Old figure Resolved value Action
Stator §2 "5A peak" 5.0 A 2.05 A worst-case typical ✔ Complete - Stator §2 updated to 2.05A worst-case typical; 5A figure retired
Controller↔Stator dock capacity 5.5 A Not the bottleneck - hybrid Molex dock remains above the 3.0 A LDO limit ✔ Complete - Samtec Link-Beta constraint retired by DEC-038
Rotor x30 claim "4.5A" 4.5 A 1.65 A (30 x 55 mA budget; 1.63 A typ) ✔ Complete - Rotor DR-ROT-06 and §3.1 now use the 54.2 mA typical / 55 mA budget figure; 150 mA figure retired
Shunt resistor Stator: 20 mΩ, Controller: 10 mΩ 10 mΩ CSS2H (Stator R1 = CSS2H-2512R-R010ELF; Controller has no shunt) ✔ Complete - Stator R1 updated to CSS2H-2512R-R010ELF (10mΩ, 2512 Kelvin)

INA219 shunt selection rationale (10 mΩ CSS2H-2512R-R010ELF):

  • V_drop at 2.05A: 2.05 x 0.010 = 20.5 mV - within INA219 ±80 mV PGA range.
  • V_drop at 3.00A max: 3.00 x 0.010 = 30 mV - within ±80 mV range.
  • Resolution: with 12-bit ADC at ±80 mV range, LSB = 2x80mV/4096 ≈ 39 µV/LSB → I_LSB = 39µV/0.010Ω ≈ 4 mA current resolution.
  • Power dissipation at 2.05A: 2.05² x 0.010 = 42 mW - 2512 Kelvin package (rated ≥0.5W) is adequate with >10x margin.
  • Power dissipation at 3.00A max: 3.00² x 0.010 = 90 mW - 2512 Kelvin package ≥0.5W still OK.
  • CAL register: 0x0400 (1024) - unchanged. CAL = 0.04096 / (Current_LSB x R_SHUNT) = 0.04096 / (0.004 x 0.010) = 1024 ✔
  • Part: CSS2H-2512R-R010ELF (Bourns 2512 Kelvin-sense, 10mΩ ±1%, 5A). Used on PM R10 (LTC3350 RSENSE), PM R16 (INA219 U10, 0x40, 5V_MAIN monitoring) and Cypher Board R1 (INA219 U2, 0x40, rotor-stack monitoring — same address as PM's U10, safe since the two devices are on independent I²C buses; see DEC-101). Total build qty: 3.

5V_MAIN Load Analysis

Consumer Current Notes
CM5 (Raspberry Pi Compute Module 5) 5.0 A max CM5 boot-to-load current profile; 25W at 5V = 5A
3V3_ENIG LDO quiescent (TPS75733KTTRG3) 2.05 A Sourced from 5V_MAIN; P_in = 5V x 2.05A = 10.25W
Status LEDs, RJ45, misc. 0.1 A
USB 3.0 external devices (TPS2065C rated max) 1.60 A System boundary: connected USB device load; TPS2065C hard-limits output
HDMI sink device 0.05 A System boundary: connected HDMI sink; AP2331W-limited
User Settings Module indicator rail (via Controller↔Stator dock → J13) 0.10 A Bank 1 only (5 LEDs x 20mA = 100mA max); Bank 2 (CFG_REFMAP switches/LEDs) removed 2026-08-16 - see User_Settings_Module/Design_Spec.md §1 and this board's own §11/§12
Cypher-Input LED bank (via Cypher Board dock, 64-Character variant worst case) 1.26 A 42 LEDs x 3 colour channels x 10mA, all channels simultaneously active (mixed colour, e.g. white/yellow/cyan); broadcast onward to whichever Cypher-Output board is installed - see Cypher-Input/Design_Spec.md §5/§7
Cypher-Output LED bank (via Cypher Board dock, any variant - worst case is variant-independent) 0.03 A Only one lens position is ever lit at a time (one-hot decode); 1 lens x 3 colour channels x 10mA, all channels simultaneously active (mixed colour); local 5V_MAIN-sourced colour-bank switching (U1-U3) - see Cypher-Output/Design_Spec.md §4/§7
Stack-Input Board solenoid actuation (via Cypher Board J4 power dock → mini-stack 5V_MAIN, one native instance per mini-stack) 0.50 A Placeholder worst-case figure carried forward from the retired Controller-side Actuation Module budget (DEC-100 relocated the physical host dock only, not the power draw); solenoid driver circuit and actual current are still TBD in Stack-Input/Design_Spec.md §4 pending a future design discussion - revisit once finalised
Total 5V_MAIN worst case (system boundary) 10.69 A
LMQ61460-Q1 dual-phase capacity 12.0 A 89.1% utilisation (10.69/12.0) - reduced margin, see note below

Scope note: The 7.15 A board-level budget (internal consumers: CM5 + LDO + misc) covers internal consumers only. External device loads (USB 3.0 + HDMI) plus the Stator-fed User Settings Module load, the Cypher-Input and Cypher-Output LED bank loads, and the Stack-Input solenoid load add 3.54 A, giving a system total of 10.69 A. Component utilisation figures (e.g. LMQ61460-Q1) are calculated against the 10.69 A system total.

Reduced margin note (2026-08-16, updated 2026-08-17): adding the Cypher-Input LED bank's worst-case 1.26 A (64-Character variant, all 3 colour channels simultaneously active) raises total utilisation from 79.2% to 89.7% of the LMQ61460-Q1's 12.0 A dual-phase capacity - still within capacity, but with materially less headroom than before. This worst case assumes a mixed colour (not a single primary channel) is selected and every LED position is populated (64-Character variant, the largest); the 26-Char Classic and 10-Numeric variants draw proportionally less (0.78 A and 0.36 A worst case respectively). Cypher-Output's own LED bank was also previously unbudgeted (found 2026-08-17) but adds only a further 0.03 A worst case, since only one Cypher-Output lens is ever lit at a time regardless of variant (unlike Cypher-Input's whole-key-bank illumination) - this brought total utilisation to 89.9% at the time. Current utilisation is 89.1% (see Document History below for the intervening changes). Revisit this margin once the LED part is confirmed (see merge-missing-components.md) and actual per-channel current is finalised - 10mA/channel is a target, not a measured figure. Separately, the User Settings Module row above was corrected from 0.24 A to 0.10 A this same session, reflecting the removal of Bank 2 (CFG_REFMAP switches/ LEDs) - see DEC-089 and User_Settings_Module/Design_Spec.md §1; this row previously carried a stale pre-removal figure.

Stator dock 5V margin: The Stator-facing 5V branch uses four large 5V_MAIN blades on the dedicated Molex J4 dock, with additional return capacity in the companion ground blades / guards. The current downstream budget remains 0.74 A, so the dock is not the limiting factor for Stator-side 5V peripherals.

Document History

Date Change
2026-04-05 Initial document - created to resolve STA-05/STA-06/ROT-04/PM-05 inconsistencies
2026-08-16 Added Cypher-Input LED bank to the 5V_MAIN Load Analysis table (1.26 A worst case, 64-Character variant, all 3 colour channels active) - was previously unbudgeted. Corrected User Settings Module indicator rail from a stale 0.24 A to 0.10 A, reflecting Bank 2 (CFG_REFMAP) removal earlier this session (DEC-089). Total 5V_MAIN worst case revised from 9.50 A to 10.76 A, LMQ61460-Q1 utilisation from 79.2% to 89.7%
2026-08-17 Added Cypher-Output LED bank to the 5V_MAIN Load Analysis table (0.03 A worst case, variant-independent since only one lens is ever lit at a time) - was previously unbudgeted; discovered while fixing an incorrect "not consumed by this board's own circuitry" claim in Cypher-Output/Design_Spec.md §6. Total 5V_MAIN worst case revised from 10.76 A to 10.79 A, LMQ61460-Q1 utilisation from 89.7% to 89.9%
2026-09-04 Relocated the "servo rail" line from a direct Controller-side draw (via the now-retired Controller J11 AM host dock, DEC-100) to "Stack-Input Board solenoid actuation" (via Cypher Board J4 power dock → mini-stack 5V_MAIN) - the actuator itself was never removed from the system, only its physical host dock moved off the Controller. Figure retained as a 0.50 A placeholder pending the still-TBD solenoid driver circuit in Stack-Input/Design_Spec.md §4. Total 5V_MAIN worst case unchanged at 10.79 A
2026-09-08 Corrected the shunt-part note: Cypher Board R1's INA219 (U2) I2C address changed from 0x45 to 0x40, matching the shunt-selection rationale text to the new address (see DEC-101)
2026-09-11 Added a placeholder 3V3_ENIG line for Stack-Input's native STM32G071K8T3TR MCUs (30 mA, 6x 5 mA conservative estimate derived from the local stm32g071.md datasheet's Run-mode IDD table) - this consumer had never been budgeted (a pre-existing gap predating this session, unrelated to the recent Controller/Cypher dock rework). Typical total revised from 2,163 mA to 2,193 mA; rounded budget 2.17 A → 2.20 A; LDO headroom 28% → 27%
2026-09-11 Moved FT232H's full current draw (100 mA) from 5V_MAIN to 3V3_ENIG, consolidating the previously-split VCCIO-only (10 mA, 3V3_ENIG) / VCC (100 mA, 5V_MAIN via the now-nonexistent 5V_USB net) entries into one 100 mA 3V3_ENIG line - see DEC-102 (FT232H now self-powered from 3V3_ENIG via Rev C VREGIN, no 5V rail required). 3V3_ENIG typical total revised from 2,193 mA to 2,283 mA (rounded 2.20 A → 2.29 A; LDO headroom 27% → 24%). 5V_MAIN total revised from 10.79 A to 10.69 A (LMQ61460-Q1 utilisation 89.9% → 89.1%)