Electronics Controller Board Layout - thepinkmile/Enigma-NG GitHub Wiki

Controller Board Layout Visualisations

Status: In Review Project: Enigma-NG Author: Izzyonstage & GitHub Copilot Version: v.0.1.0 Associated Hardware Revision: Rev A Last Updated: 2026-09-04

1. Rear Dock Interfaces

The Controller is the fixed motherboard of the enclosure and carries both removable-board docks:

  • J1 / J2 / J3 - three TE 10-position connectors to the Power Module
  • J4 - Molex EXTreme Guardian HD hybrid connector to the Cypher Board (power-only)
  • J5 - Samtec QSS-025 vertical female connector to the Cypher Board (signal-only)
rear edge of Controller

 [ J4 ] [ J5 ]   [ J1 ] [ J2 ] [ J3 ]
  to Cypher          to Power Module

2. Controller ↔ Power Module Dock

2.1 J1 - Main Regulated Rails

Allocation Notes
3 x 5V_MAIN Primary regulated 5V feed from PM to Controller
2 x 3V3_ENIG Clean logic rail feed from PM to Controller
5 x GND Shared return path

Connector family: TE 1-1674231-1 (Controller receptacle) ↔ 1123684-7 (PM plug), 10 positions, 2.5 mm pitch, 6 A/contact.

Reference datasheets: TE-1-1674231-1-datasheet.md, TE-1123684-7-datasheet.md

2.2 J2 - PoE Auxiliary Feed

Allocation Notes
3 x VIN_POE_12V Regulated PoE-derived 12V-class auxiliary feed from Controller PoE front-end into PM OR-ing stage
7 x GND Shared return path

2.3 J3 - Low-Speed Control / Telemetry

Signal Direction Notes
I2C0_SDA Bidir PM-dedicated I²C bus (Bank 0); shared PM telemetry and PM-local GPIO-expander bus
I2C0_SCL Bidir PM-dedicated I²C bus (Bank 0); shared PM telemetry and PM-local GPIO-expander bus
PM_IO_INT_N PM -> CTRL Active-low interrupt from PM PCA9534APWR
PWR_GD PM -> CTRL Direct rail-health telemetry from MCP121T
ROTOR_EN_N CTRL -> PM Direct 3V3_ENIG LDO enable control
PWR_BUT_N PM -> CTRL Direct CM5 PMIC power-button path
LED_PWR_N CTRL -> PM Direct CM5 power-state indication for the SW2 hardware LED logic
3 x GND - Guards / return path

3. Controller ↔ Cypher Dock

3.1 J4 - Power-Only Dock (Molex 2195630015 / 2195620015)

Zero signal contacts. See DEC-098.

Contact type Allocation Notes
Power-pitch (5x, big pins) 5 x GND GND mates first on the larger, more robust contacts
Signal-pitch (8x) 8 x 5V_MAIN 4.5A/contact rating (Molex 2141130000-PS-000 §4.2) — 36A theoretical capacity
Signal-pitch (7x) 7 x 3V3_ENIG 4.5A/contact rating — 31.5A theoretical capacity

Connector family: Molex 2195630015 receptacle on Controller ↔ 2195620015 plug on Cypher.

Reference datasheets: Molex-2195630015-datasheet.md, Molex-2195630015-drawings.md, Molex-2195620015-datasheet.md, Molex-2195620015-drawings.md, Molex-ExtremeGuardianHD-2141130000-PS-000-specification.md

3.2 J5 - Signal-Only Dock (Samtec QSS-025-01-L-D-A-GP-K / QTS-025-01-L-D-RA-P)

Zero power rails. See DEC-098. 50 contacts: 2 center-GND-bar (1/row) + 24 usable pins/row. Pin numbering: column Cn, top pin = 2n-1, bottom pin = 2n. Note: the connector's internal ground wedge runs the full connector length between the top (odd) and bottom (even) pin rows — top/bottom crosstalk within a column is inherently shielded; the exposure to guard against is column-to-column (same-row) adjacency, hence the GND separator columns below.

Top Row Signal Top Pin# Bottom Pin# Bottom Row Signal
GND 1 2 GND
PWM0[0] 3 4 GND
GND 5 6 PWM0[1]
PWM0[2] 7 8 GND
GND 9 10 PWM0[3]
GND 11 12 GND
GND 13 14 GND
GPCLK[0] 15 16 GPCLK[1]
GND 17 18 GND
GND 19 20 GND
USB_D_PLUS 21 22 USB_D_MINUS
GND 23 24 GND
GND (bar) 25 26 GND (bar)
GND 27 28 GND
GND 29 30 GND
I2C1_SDA (Bank 1, Cypher peripherals — existing) 31 32 I2C1_SCL (Bank 1, existing)
GND 33 34 GND
I2C2_SDA (Bank 2, future) 35 36 I2C2_SCL (Bank 2, future)
GND 37 38 GND
I2C3_SDA (Bank 3, future) 39 40 I2C3_SCL (Bank 3, future)
GND 41 42 GND
I2C4_SDA (Bank 4, future) 43 44 I2C4_SCL (Bank 4, future)
GND 45 46 GND
I2C6_SDA (Bank 6, spare/HID-future) 47 48 I2C6_SCL (Bank 6, spare/HID-future)
GND 49 50 GND

Note: I2C0 (PM-dedicated bus) is not present on this connector — it is routed exclusively via J3 to the Power Module (see §2.3). This connector carries only I2C1 (active) plus I2C2/I2C3/I2C4/I2C6 (reserved/NC on the Cypher Board for future expansion). See DR-CTL-13, DEC-099.

Connector family: Samtec QSS-025-01-L-D-A-GP-K (vertical female) on Controller ↔ QTS-025-01-L-D-RA-P (right-angle male) on Cypher.

Reference datasheets: Samtec-QSS-Qualification_test-Report.md, Samtec-QSS-QTS-RA-Characterisation-Test-Report.md, Samtec-QSS-QTS-RA-Power-Test-Report.md

J4 and J5 are split strictly by electrical function: J4 carries all power/return (no signals), J5 carries all signals/GND (no power rails) — see DEC-098.

4. External I/O Placement

right edge of Controller

 [ RJ45 + PoE front-end ]
 [ USB 3.0 stacked Type-A ]
 [ HDMI ]
  • The Controller owns the RJ45, Ethernet ESD, magnetics, and PoE PD / ACF front-end. The PoE front-end passes its regulated auxiliary feed into the Power Module over J2.
  • J9 and J10 are internal-only connectors and are not part of the external I/O edge. J9 sits between J5 and the Power Module mounting area so it can route by ribbon cable into the future in-lid touchscreen assembly, while J10 serves the CM5 active-cooler heatsink fan.

5. Placement Summary

rear / dock edge
 _______________________________________________________________________
|  [J4]        [J5]              [J9]         | (Power Module mounting) |
|  (power)    (signal)          (display)     | [J1]               [J3] |
|                          _________________  |          [J2]           |
|                         |                 | |_________________________|
|                         |      CM5        |                           |
|                         |     Module      |                           |
|                         | [ Low-Profile ] |                    [RJ45] |
|                         | [    Area     ] |                    [USB3] |
|                         |_________________|                    [HDMI] |
|_______________________________________________________________________|
left side / internal                                           right side

The Controller is the only board that must be inserted as the enclosure reference part. The Power Module and Cypher Board then dock into it as mechanically independent service modules. J4 (power dock, left-middle) and J5 (signal dock, towards centre) are both mounted horizontally, matching the CM5's own horizontal orientation (right-middle, with Ethernet/USB/HDMI hugging the right edge). Exact XY placement is finalised at PCB layout time.

6. CM5 Module Carrier (J13, J14, MH13–MH16)

The CM5 Compute Module 5 mounts on the Controller via two Amphenol 10164227-1004A1RLF carrier sockets (J13, J14) and four SMT standoffs (MH13–MH16).

6.1 J13 and J14 — CM5 Module Carrier Connectors

  • Part: Amphenol 10164227-1004A1RLF — CM5 carrier socket, 4.0mm stack height.
  • Placement: J13 and J14 are placed in the central board region beneath the CM5 module footprint. Both connectors must be positioned to align with the CM5 module edge connector interface per the Raspberry Pi CM5 mechanical drawing. Trace routing and copper fills are permitted in the CM5 shadow area; active or tall components are not (see §6.2 height rule).
  • Stack height: 4.0mm from Controller PCB surface to the underside of the CM5 module PCB.
  • Cross-ref: design/Electronics/Controller/Design_Spec.md §2.3; BOM J13, J14.

6.2 MH13–MH16 — CM5 Carrier Standoffs

  • Part: Wurth Elektronik 9774040151R — M2.5×4.0mm SMT standoff; four instances.
  • Function: Mechanical standoffs that set the 4.0mm stack height for J13/J14 and provide rigidity under the CM5 module.
  • GND: MH13–MH16 pads shall be connected to GND — not GND_CHASSIS. See design/Standards/Global_Routing_Spec.md for module mounting hole grounding rules.
  • Placement: Four corners of the CM5 module footprint shadow; exact XY positions TBD at PCB layout, must mirror the CM5 module mechanical reference pattern.
  • Component height rule: Maximum installed component height within the CM5 shadow area is 2.0mm above the Controller PCB surface. Only low-profile passive components are permitted beneath the CM5; active ICs, connectors, test points, and exposed via pads are prohibited.
  • Cross-ref: design/Electronics/Controller/Design_Spec.md §2.3; BOM MH13–MH16.

7. PoE ACF Front-End Placement (T1, Q1, Q2, L1, C17, C20)

The PoE ACF Forward front-end occupies the right-edge zone of the board, clustered around the RJ45 magnetics jack and the two PoE ICs (U7 TPS2372-4RGWR, U8 TPS23730RMTR). GbE ESD arrays U5 and U6 are also in this zone.

7.1 Component Summary

RefDes Part Role
T1 TDK B82806D0060A120 ACF Forward PoE PD transformer
U7 TPS2372-4RGWR PoE PD interface controller
U8 TPS23730RMTR ACF Forward gate-drive controller
Q1 STD25NF20 ACF primary switch (GATE_P), DPAK
Q2 STD25NF20 ACF active clamp switch (GATE_C), DPAK
L1 PA4343.333NLT 33µH ACF forward output inductor
C17 C0805C223K2RACAUTO 22nF 200V 0805 ACF primary-side clamp capacitor (Cclamp)
C20 (×4) CGA9N3X7R1E476M230KB 47µF 25V 2220 ACF output filter capacitors (4× in parallel)

7.2 Placement Notes

  • Zone: Right edge of the Controller PCB directly adjacent to the RJ45 magnetics jack. U7 and U8 shall be placed as close as practical to T1 to minimise the primary-side switching loop area.
  • Q1 and Q2 (DPAK): Both DPAK exposed tabs shall be tied to GND with a copper pour and via stitching for thermal dissipation. Q1 and Q2 shall be placed on the primary side of T1 to keep the primary-side switching loop compact. Gate-drive traces from U8 GATE_P to Q1 and from U8 GATE_C to Q2 shall be as short and direct as practical.
  • T1 solder bridge note: The TDK B82806D0060A120 datasheet permits optional solder bridges between pins 1–2 and between pins 7–8 to parallel primary-side winding pairs for lower resistance. Confirm at schematic capture whether the ACF Forward circuit uses those pins separately before deciding whether to apply the solder bridges in the PCB layout.
  • L1 (PA4343.333NLT): 13.5mm × 12.5mm × 6.2mm shielded ferrite SMT inductor. Place on the secondary side of T1 on the VIN_POE_12V output rail, between T1 and C20. Orient the winding terminals toward T1 to minimise secondary-side loop length.
  • C17 (0805): Place in the U8 primary-side active-clamp loop between the clamp switch node and GND, within 5mm of U8. 200V rating is required for the primary-side environment.
  • C20 (4× 2220): Four CGA9N3X7R1E476M230KB in parallel on VIN_POE_12V at the LC filter output. Arrange in a 2×2 grid on the secondary side of L1 with a common pour to VIN_POE_12V.
  • Cross-ref: design/Electronics/Controller/Design_Spec.md §6.1; DR-CTL-17 to DR-CTL-22; design/Electronics/Controller/PoE_Power_Analysis.md.

8. Chassis Mounting Holes (MH1–MH4)

Follows GRS §4.3 Pattern A — exact XY positions TBD at PCB layout per GRS §4.2.

  • Count: 4× M3 PTH mounting holes (one near each corner)
  • Hole diameter: Ø3.2mm (clearance for M3 fastener)
  • Net: GND_CHASSIS — bonded to chassis ground per GRS §4
  • BOM: No BOM entry; plain chassis mounting holes with no fitted components
  • Cross-ref: design/Electronics/Controller/Design_Spec.md DR-CTL-18; design/Standards/Global_Routing_Spec.md §4.3