Design Log index - thepinkmile/Enigma-NG GitHub Wiki
Enigma-NG Design Decision Log
Status: Active Project: Enigma-NG Author: Izzyonstage & GitHub Copilot Version: v.0.1.0 Associated Hardware Revision: Rev A Last Updated: 2026-09-17
This file records key architectural and component decisions made during the design of the Enigma-NG system. Each entry captures the decision taken, the rationale behind it, the alternatives that were considered, and any constraints or caveats that future designers should be aware of.
Entries are numbered sequentially as DEC-NNN. Where a decision supersedes a previous one, the earlier entry is updated with a cross-reference.
| DEC | Title | Date | Status | Summary |
|---|---|---|---|---|
| DEC-001 | 3V3_ENIG Used Throughout; 3V3_SYSTEM Removed from BtB Interconnect | 2025 | Obsolete - superseded by DEC-037 | The 3V3_SYSTEM rail (sourced from the CM5 on the Controller Board) is not routed to the Power Module over the Link-... |
| DEC-002 | PoE Option A2 Selected: Coilcraft POE600F-12LD | 2025 | Decided | The PoE transformer T2 uses a Coilcraft POE600F-12LD off-the-shelf ACF transformer (12V output, 60W, 200kHz, ≥1500Vrm... |
| DEC-003 | PoE Output 12V; OR-ing Priority Logic Required | 2025 | Decided | PoE outputs 12V (not 15V) into the OR-ing stage. |
| DEC-004 | Supercap Charge Current 0.5A Under PoE | 2025 | Superseded by DEC-029 (cell specification updated; 0.5A charge current constraint retained) | When running on PoE (802.3bt Type 4, 72W budget), the supercap charge current is reduced to 0.5A (vs. |
| DEC-005 | TPS25980 eFuse Replaces TPS259474L | 2025 | Decided | The input eFuse uses a TPS25980 (7A ILIM, silicon-fixed 16.9V OVLO) rather than the originally considered TPS259474L... |
| DEC-006 | STUSB4500 Negotiates 15V/5A (75W) | 2025 | Decided | The STUSB4500 standalone PD sink is programmed to negotiate 15V/5A (75W) from the wall adapter or USB-C PD source. |
| DEC-007 | Dual Interleaved LMQ61460-Q1 5V Buck (12A) | 2025 | Decided | Two LMQ61460-Q1 buck regulators are used in a dual interleaved configuration, providing a combined 12A output at 5V. |
| DEC-008 | TPS25750 Emulates 5V/5A PD Profile to CM5 | 2025 | Superseded by DEC-012 | The TPS25750 PD emulator advertises a 5V/5A profile to the CM5 internal USB-C port. |
| DEC-009 | Legacy Controller Probe-Access Pin 14 Reassigned to SW_LED_CTRL | 2025 (GND); superseded by final design (SW_LED_CTRL) | Decided | The legacy Controller probe-access concept pin 14 was initially reassigned from 3V3_SYSTEM to GND, following the re... |
| DEC-010 | INC-14 DEFERRED: Legacy Probe-Access ESD Protection (Post-Prototype) | 2025 | Deferred - Accepted risk for prototype stage | ESD protection on the historical probe-access concept is deferred to post-prototype evaluation. |
| DEC-011 | All Power Rails on Power Module; 3V3_ENIG Serves Rotor Stack | 2025 | ✔ RESOLVED | All power rails are generated on the Power Module. |
| DEC-012 | U4 TPS25750 Replaced with TPS25751DREFR (NRND Resolution) | 2026-04-03 | ✔ RESOLVED | Replace TPS25750 (NRND - Not Recommended for New Designs) with TPS25751DREFR (PD3.1 certified DRP controller, WQFN-38... |
| DEC-013 | L3 EMI Inductor Changed to Bourns SRP1265A-100M | 2026-04-03 | ✔ RESOLVED | Replace Wurth 7447789100 with Bourns SRP1265A-100M as L3 (EMI DM Pi-filter inductor). |
| DEC-014 | Controller Board Uses ERF8 (Female) on Both BtB Connectors for Blind-Mate Assembly | 2026-04-04 | ✔ RESOLVED | Both BtB connectors on the Controller Board use the ERF8 female socket: J1 (Link-Alpha) uses ERF8-040-05.0-S-DV-K-TR... |
| DEC-015 | LINK-BETA Connector Reduced from 80-pin to 40-pin (ERF8-020 / ERM8-020) | 2026-04-04 | ✔ RESOLVED | The LINK-BETA Board-to-Board connector is reduced from 80-pin (ERF8-040 / ERM8-040) to 40-pin (ERF8-020-05.0-S-DV-K-T... |
| DEC-016 | JTAG Controlled Impedance and Series Termination | 2026-04-05 | ✔ ADOPTED | All JTAG signal traces on 4-layer and 6-layer PCBs are specified at 50 Ω controlled impedance (0.127 mm / 5 mil trace... |
| DEC-017 | Minimum 4-Layer Stackup for All Non-Controller Boards | 2026-04-05 | ✔ ADOPTED | All PCBs in the Enigma-NG system shall use a minimum of 4-layer stackup (JLCPCB JLC04161H-7628). |
| DEC-018 | Connector Pinout Ownership Model | 2026-04-05 | Adopted | Each multi-board connector interface shall have a single Definition Owner - the board whose Board_Layout.md (or `De... |
| DEC-019 | PoE Transformer Topology: ACF (Option A) Selected | 2026-04-05 | ✔ Adopted | The Power Module retains the Active Clamp Flyback (ACF) topology with the Coilcraft POE600F-12LD transformer. |
| DEC-020 | GND_CHASSIS Rib Clearway ENIG Bond | 2026-04-08 | Accepted - 2026-04-08 | The 3.0mm rib clearway gaps between supercap cells shall have: |
| DEC-021 | Supercapacitor Bank Upgrade: 2x2 2S2P → 2x3 2S3P | 2026-04-08 | Superseded by DEC-029 (arrangement 2S3P retained; cell capacitance updated 22F → 25F Abracon) | The supercapacitor bank is upgraded from a 2x2 (4-cell, 2S2P) to a 2x3 (6-cell, 2S3P) arrangement, with the inter-cel... |
| DEC-022 | JDB FT232H Clock Source: Dedicated 12MHz SMD Crystal Selected | 2026-04-06 | Obsolete - superseded by DEC-037 | Dedicated 12MHz SMD passive crystal (Y1) on the JDB PCB. |
| DEC-023 | JDB GND_CHASSIS Omitted; Mounting Holes Tied to GND | 2026-04-06 | Decided | The JTAG Daughterboard (JDB) does not implement a GND_CHASSIS net. |
| DEC-024 | JDB is Complete JTAG Master; Controller JTAG Lines Are Pass-Through | 2026-04-06 | Decided | The JTAG Daughterboard (JDB) is the complete JTAG master. |
| DEC-025 | CM5 Shutdown Mechanism: Hardware-Driven; LTC3350 Software Support Deferred | 2026-04-09 | Deferred - Software PoC Stage | The final implementation of the CM5 graceful shutdown mechanism is hardware-driven via the LTC3350 /INTB -> MIC1555... |
| DEC-026 | Rotor Position Encoder: AS5600 Replaced with Single-Track Capacitive Encoder | 2026-04-12 | Accepted | The AMS AS5600 magnetic encoder (originally specified in DR-ROT-03) is replaced with a single-track absolute capaciti... |
| DEC-027 | Rotor Position Readback via JTAG Virtual JTAG (USER0 UDR) | 2026-04-12 | Accepted | The CPLD on each rotor must expose the effective rotor position (STGC-decoded position + SW1 ring offset, mod N) via... |
| DEC-028 | Split dual-board rotor architecture | 2026-04-14 | Accepted | The rotor is split into two circular PCBs (Board A input side, Board B output side), each Ø92mm, connected by four si... |
| DEC-029 | Supercapacitor Hold-Up Specification: 25F Abracon Cells, 2S4P, ≥20 s at 15W | 2026-04-14 | Accepted - 2026-04-14 | The supercapacitor hold-up minimum requirement is ≥20 seconds at a 15W shutdown load (CM5 typical operating current:... |
| DEC-030 | 5V_MAIN Backup Switchover Transient Fix (R14, R30, C35) | 2026-04-14 | Accepted | - |
| DEC-031 | CM5 Virtual Keyboard (Key Injection) Feature Architecture | 2026-04-14 | Decided | Add three I²C expanders to the Stator board on the shared I²C-1 bus: |
| DEC-032 | Settings Board: Panel-Mount Configuration Controls with CM5 Override | 2026-04-14 | Decided | 1. |
| DEC-033 | DSI1 Display Connector Provision for Optional Lid Touchscreen | 2026-04-14 | Decided | 1. |
| DEC-034 | Switch Hardware Refresh: Settings Board Toggle + Discrete RGB LED, Ruggedized PM SW1 | 2026-04-16 | Decided | 1. |
| DEC-035 | HID Keyboard and Lightboard Use a 40-Position QWERTY-Derived Layout for the 64-Character Code Space | 2026-04-17 | Decided | 1. |
| DEC-036 | LINK-BETA Former Monitor Pins Reallocated as Grouped Power Rails | 2026-04-18 | Decided | Retain the 40-pin LINK-BETA connector and apply this active allocation: |
| DEC-037 | LINK-BETA Pin Map Regrouped Around Dedicated JTAG and I2C Guard Bands | 2026-04-18 | Decided | Adopt this LINK-BETA allocation as the active mapping: |
| DEC-038 | Controller-Centric Dock Architecture Replaces Legacy Link-Alpha / Link-Beta Backplane | 2026-04-19 | Decided | #### 1. |
| DEC-039 | Enclosure-Connected Boards Use GND_CHASSIS; Daughterboards Are Exempt | 2026-04-20 | Decided | 1. |
| DEC-040 | Diagnostics Banks Removed from Active Design Specs Pending Coupon Review | 2026-04-25 | Decided | 1. |
| DEC-041 | Encoder Modules Use EPM570 with Digital Debounce and Role-by-Programming | 2026-04-26 | Decided | 1. |
| DEC-042 | Encoder Port Pin 8 Carries HID-Local ENC_ACTIVE_N |
2026-04-26 | Decided | 1. |
| DEC-043 | Shared Actuation Module Replaces Direct Controller Servo GPIO | 2026-04-26 | Decided | 1. |
| DEC-044 | FDC2114 Internal Oscillator Selected (CLKIN → GND) | 2026-04-26 | Decided | Use the FDC2114 internal oscillator (CLKIN → GND). |
| DEC-045 | Rotor Samtec ERM8/ERF8 Connectors Require ESD Protection | 2026-04-28 | Decided | Add TVS/ESD protection to all Samtec ERM8/ERF8 connector interfaces on the Rotor Board. |
| DEC-046 | Bypass/Decoupling Capacitor Voltage Rating: 50V Retained on All Non-PM Boards | 2026-04-29 | Decided | Retain 50V-rated bypass and decoupling capacitors as the approved standard across all non-PM boards. |
| DEC-047 | OR-ing MOSFET Corrected to CSD17578Q5A | 2025-07-05 | Decided | Replace CSD17483F4T with CSD17578Q5A (TI NexFET N-channel MOSFET): |
| DEC-048 | ESD Protection Extended to Host-Side Rotor-Facing BtB Connectors | 2026-04-30 | Approved | All Samtec ERM8/ERF8 connector faces on host boards that are exposed during live rotor swap require a TPD4E05U06QDQAR... |
| DEC-049 | Rotor Internal Headers Renamed to J-Convention; Connector Count Updated to 8; BOM Unified | 2026-05-01 | Accepted | The four internal rotor interconnect headers previously designated H_SW3, H_PWR, H_JTAG, and H_SENS are renamed to J7... |
| DEC-050 | Encoder Blade Terminal RefDes Corrected from BT to J Convention | 2026-05-01 | Active | The 64 PCB spade blade terminals (Keystone 1285-ST) on the Encoder board have been renamed from BT1-BT64 to J3-... |
| DEC-051 | Settings Board Renamed to User Settings Module (Board Code SBD → USM) | 2026-05-02 | Active | The Settings Board is renamed to User Settings Module throughout all active design documentation, the consolidate... |
| DEC-052 | Variant-Specific FDC2114 RefDes Use A/B Suffix Convention | 2025-07-10 | Active | Variant-specific FDC2114 sensor components on the Rotor board are assigned RefDes with an A or B suffix to indicate w... |
| DEC-053 | Extension Port Connector Upgraded from BHR-20-VUA (20-pin) to 2BHR-30-VUA (30-pin) | 2025-07-10 | Active | Replace the Adam Tech BHR-20-VUA (20-pin 2x10) with the Adam Tech 2BHR-30-VUA (30-pin 2x15) on all Extension Port ins... |
| DEC-054 | Signal Net Renamed: PWR_BUT → PWR_BUT_N (Active-Low Suffix Conformance) | 2026-07-11 | Active | The signal net PWR_BUT (the power key line from the Power Module to the CM5 PMIC dedicated hardware input) is renam... |
| DEC-055 | F-108 System-Wide Reference Designator and Requirement ID Consecutive Renumbering | 2026-05-05 | Accepted | Renumber all affected component RefDes and FR/DR requirement IDs consecutively across all impacted board Design_Spec... |
| DEC-056 | Relocate Investigation Documents to Board-Owned Folders | 2026-05-04 | Accepted | Move the two investigation documents out of design/Electronics/Investigations/ and into the folders of the boards t... |
| DEC-057 | Daughterboard Mounting Hole Specification and Standoff BOM Ownership | 2026-05-05 | Accepted | This is the single authoritative reference for mounting hole specification and standoff BOM ownership across all boar... |
| DEC-058 | JDB Connector Upgrade: Hat-Headers to DF40C-20 BtB | 2026-05-15 | Accepted | Replace J1 + J2 hat-header connectors with a single Hirose DF40C-20DP-0.4V(51) 20-pin board-to-board plug on the JDB,... |
| DEC-059 | ERM8/ERF8 Stacking Height Confirmed; Rotor Stack Assembly Specification Created | 2026-05-28 | Confirmed | The -05.0- lead style designation in the selected parts: |
| DEC-060 | JTAG Daughterboard Renamed to JTAG Module; JDB Prefix Replaced with JM | 2026-05-07 | Confirmed | The board is renamed from JTAG Daughterboard to JTAG Module with immediate effect: |
| DEC-061 | Pass 7 Review Corrections: CTL/STA/ROT/ENC/AM/GRS/Status Updates | 2026-05-08 | Confirmed | Apply all eight corrections as described above. |
| DEC-062 | CTL PoE T1 Selection: TDK B82806D0060A120; Topology ACF Flyback → ACF Forward | 2025-07-10 | Confirmed | 1. |
| DEC-063 | CTL PoE L1 Selection: Yageo PA4343.333NLT (ACF Forward Output Inductor) | 2026-05-09 | Confirmed | L1 selected: Yageo PA4343.333NLT. |
| DEC-064 | CTL PoE C17 Final Part Selection: Kemet C0805C223K2RACAUTO (22nF 200V X7R 0805) | 2026-05-09 | Confirmed | C17 selected: Kemet C0805C223K2RACAUTO (22nF, 200V, X7R, 0805, ±10%, AEC-Q200). |
| DEC-065 | System-Wide Stackup Code Correction and JLCPCB-Authoritative Impedance Values | 2026-05-11 | Confirmed | Correct 4-layer stackup code: JLC041621-3313 Correct 6-layer stackup code: JLC061621-3313 |
| DEC-066 | GRS Canonical PCB Stackup Authority (Consolidation) | 2026-05-11 | Confirmed | Stackup definitions are consolidated into the Global Routing Specification as new section §2.3 PCB Stackup Definition... |
| DEC-067 | AM SW1/SW2 Tactile Switch Rating Accepted for Production | 2026-05-12 | Confirmed | SW1 and SW2 shall remain as the Omron B3F-1070 (or equivalent SPST NO through-hole tactile switch) for production. |
| DEC-068 | PM Per-Input Bulk Capacitors and Output Source-Quality Bulk Banks | 2026-05-12 | Confirmed | Q1 - Pre-OR-ing per-input bulk: Each of the three input paths shall have a tight parallel cluster of 3× Samsung CL32B... |
| DEC-069 | PM Per-Input Polyfuse Protection and UVLO Resistor Recalculation | 2026-05-14 | Confirmed | D1 - Per-input polyfuse: Each of the three input paths (VIN_POE_12V, Battery, USB-C) shall have a Bel Fuse 0ZRB0600FF... |
| DEC-070 | MCP23017 I²C Silicon Restriction: GPB[7]/GPA[7] Review and CFG_APPLY_N Reassignment | 2026-05-13 | Confirmed | D1 - CFG_APPLY_N reassignment: CFG_APPLY_N on USM U1 shall be reassigned from GPB[7] to GPA[6]. |
| DEC-071 | USM SPDT Switch Dual-Terminated Wiring and Pull-Down Resistor Removal | 2026-05-14 | Confirmed | D1 - Dual-terminated switch wiring adopted; pull-down resistors removed: Each toggle switch (SW1-SW10) is wired as fo... |
| DEC-072 | Review Pass 9 Findings and Resolutions | 2026-05-14 | Accepted | Review Pass 9 identified 75 findings across all boards. |
| DEC-073 | LTC3350 RT Resistor Correction: 33.2 kΩ → 133 kΩ (Amends DEC-030) | 2026-05-15 | Accepted | R23 (LTC3350 RT frequency-setting resistor) is changed from 33.2 kΩ to 133 kΩ (E96 nearest value to 133.75 kΩ). |
| DEC-074 | Rename CPLD Reset Signal: SYS_RESET_N → CPLD_RESET_N | 2026-05-16 | Accepted | The active-low CPLD reset signal previously named SYS_RESET_N is renamed to CPLD_RESET_N across all design documentat... |
| DEC-075 | TPS25751 Option C: External EEPROM + Isolated I2Ct Debug Header on Power Module | 2026-05-16 | Accepted | Implement Option C: |
| DEC-076 | PM 3V3 Architecture Redesign: 3V3_MAIN/3V3_ENIG Rail Split, J4 Dual-Purpose Programming, J6 Removal, and Q12 Parallel P-FET Selection | 2026-05-16 | Accepted | A four-part redesign resolves both issues. |
| DEC-077 | Retrospective: Rotor TTD Daisy-Chain - No Series Termination Resistors (Amends DEC-016) | 2026-05-18 | Accepted | The deviation from DEC-016 for Rotor J2/J5 TTD lines is accepted retrospectively. |
| DEC-078 | CPLD_RESET_N Stator Buffer: BSS138 N-Channel MOSFET (New Decision; References DEC-077) | 2026-05-18 | Accepted | A BSS138 N-channel MOSFET buffer is added to the Stator board as new reference designator Q1 on the CPLD_RESET_N line: |
| DEC-079 | C20 Voltage Rating Correction: 25V → 35V (Amends DEC-072 BOM Item 1) | 2026-05-18 | Accepted | C20 is corrected to: |
| DEC-080 | Retrospective: PM and Stator Dock Connector Redesignation (Amends DEC-038) | 2026-05-18 | Decided | #### Controller Board |
| DEC-081 | Retrospective: Rotor TTD No-Series-Resistor Policy (In Addition to DEC-016) | 2026-05-18 | Decided | The Rotor Board TTD path carries no series resistor at each rotor-hop BtB interface (TTD exits the CPLD directly to... |
| DEC-082 | 10µF Bulk Reservoir Capacitor Upgrade: 25V 0805 → 50V 1206, All Boards | 2026-05-21 | Confirmed | Standardise all 10µF X7R bulk/reservoir capacitors across all boards to: |
| DEC-083 | Retire all_boards_bom.json; Consolidate BOM Authority in Design_Spec Files and Consolidated_BOM |
2026-05-21 | Confirmed | Retire all_boards_bom.json permanently. |
| DEC-084 | Cypher-Stack Architecture Migration and Board-Role Consolidation | 2026-07-04 | Confirmed | Applying all changes from extension-mechanical design discussion creating components for a new mini-stack component to replace several boards and simplify mechanical assembly and usage of the system. |
| DEC-085 | Stack-Output J4 Power-Pin 0Ω Links for Prototype Test Flexibility | 2026-07-12 | Accepted — confirm after prototype testing | Install 0Ω links R4/R5 on Stack-Output J4 power connector to enable parallel power return path; reversible if prototype testing reveals EMI issues. |
| DEC-086 | Cypher-Input Restructured into Common/Variant Files; 10-Numeric Variant Added; Single Shared I2C Address | 2026-08-12 | Decided | Split Cypher-Input into common Design_Spec/Board_Layout + per-variant files (mirrors Rotor); added 10-Numeric variant (numpad + Space/Enter); collapsed U4 to single fixed I2C address 0x38, BOARD_ROLE_ID[2:0] is the sole variant identifier. |
| DEC-087 | Cypher-Input LED Colour Architecture Moved Off plain-bits, Onto a Local RGB Colour-Select Circuit |
2026-08-14 | Decided | LED colour/brightness generation moved entirely onto Cypher-Input (never via the ENC module/plain-bits); software-configurable RGB via U4 + mux (Extended variant only); brightness via shared cathode-return switch; broadcast to Cypher-Output via left connector pair; LED part now a placeholder pending user confirmation. |
| DEC-088 | Plugboard Jacks Wired Directly to Cypher Board Spade Bank; J4/J6 Left Pair Reserves 5V_MAIN | 2026-08-16 | Decided | Plugboard board's only electrical role is passive HID JTAG-spoke termination; physical patch jacks mount on Plugboard mechanically only, wired via spade-to-spade harness directly to Cypher Board's own J20+ spade bank (bottom edge of rear face, general location only); J4/J6 left pair gains reserved 5V_MAIN pins for potential future LED use. |
| DEC-089 | BOARD_ROLE_ID Widened to 4-Bit Capability Bitmask; CPLD Pin-Freeing via JTAG UFM Write; Migration to J5 |
2026-08-16 | Decided | CFG_REFMAP[5:0] removed in favour of JTAG-based UFM reflector-map writes, freeing CPLD pins; BOARD_ROLE_ID widened from 3-bit enumerated index to 4-bit capability bitmask (Characters/Numbers/Special/Custom) with an AND-based compatibility comparator producing HID_VARIANT_ID[3:0]; strap migrated from the J6 (right) to J5 (left) HID interconnect connector; future Cypher-Output board to carry a custom-support SPDT switch next to RV1. |
| DEC-090 | Cypher Board J3 (Stack-Input Side) Full 50-Pin Allocation; ACTUATE_REQUEST_IN_N/ACTUATE_REQUEST_OUT_N Signal Pair | 2026-09-01 | Decided | J3 (Stack-Input/STA-side) fully 50-pin allocated (adds 3V3_ENIG, 5V_MAIN, ACTUATE_REQUEST_IN_N, ACTUATE_REQUEST_OUT_N); ENC_ACTIVE_N removed from J3/Stack-Input (confirmed HID-local-only, resolving a contradiction with Cypher's own spec); ACTUATE_REQUEST_N split into an IN/OUT pair present at both front and rear of every connector in the chain, CPLD-arbitrated. J4 (Stack-Output side) remains open. |
| DEC-091 | J3 ESD Protection Extended to ACTUATE_REQUEST_IN_N/OUT_N; Actuation Gating Resolved to Cypher CPLD (Amends DEC-090) | 2026-09-01 | Decided | New ESD IC U19 (extra count of TPD4E05U06QDQARQ1) protects ACTUATE_REQUEST_IN_N/OUT_N on J3; actuation-trigger gating (previously ANDed with the now-removed ENC_ACTIVE_N) resolved at the Cypher Board's own CPLD, which only asserts the signal while a key is depressed — no new hardware needed on Stack-Input. |
| DEC-092 | Cypher Board J4 (Stack-Output Side) Full 50-Pin Allocation | 2026-09-02 | Decided | J4 fully 50-pin allocated, mirroring J3's template with JTAG broadcast signals replaced by GND and 5V_MAIN consolidated into extra 3V3_ENIG pins; TTD_RETURN placed at J3's TTD pin position; ACTUATE_REQUEST_IN_N/OUT_N added, ESD covered by existing U16 spare channels (no new component). All four Cypher connectors (J3-J6) now fully allocated; ACTUATE_REQUEST routing through Rotor/Stack-Interposer boards remains an open follow-up. |
| DEC-093 | ACTUATE_REQUEST End-to-End Signal Path Defined; J4 Renamed to REF-Specific Nets; Rotor/Stack-Interposer Connectors Extended | 2026-09-02 | Decided | Full quad-pass ACTUATE_REQUEST signal path defined (mirrors the existing ENC_DATA cipher path structure); Cypher J4 actuate pins renamed to ACTUATE_REQUEST_REF_IN_N/OUT_N (amends DEC-092 naming); Stack-Input's front-OUT/rear-IN "NC" designations corrected to describe real two-pass traffic (amends DEC-090 wiring narrative); Rotor J3/J6 ENC connectors gain ACTUATE_REQUEST_IN_N/OUT_N (new ESD ICs U12/U13, extra count of existing part); Stack-Interposer J1/J2 gain SIG-BLOCK-G/H on spare pins 15/16. Stack-Output's own J1/J2 REF-side pin-by-pin review remains open. |
| DEC-094 | Connector Ownership Reassignment for Reused Chain Templates (Amends DEC-018) | 2026-09-02 | Decided | IC-STA-CHAIN (Cypher J3 / every Stack-Input J1-J2) ownership moves from Cypher to Stack-Input; IC-REF-CHAIN (Cypher J4 / every Stack-Output J1-J2) ownership moves from Cypher to Stack-Output - both because the repeatedly-instantiated board, not the singular Cypher endpoint, should own a reused chain template. IC-ROT-JTAG/ENC/PWR (Rotor) and IC-HID (Cypher) confirmed unchanged; IC-INTERPOSER (Stack-Interposer) stale "TBD" cross-reference corrected. No electrical change - documentation ownership/location only. |
| DEC-095 | ACTUATE_REQUEST ESD Protection Completed (Stack-Input, Stack-Output); Stack-Output Passive Wiring Defined | 2026-09-02 | Decided | New ESD ICs U11/U12 (Stack-Input, J1/J5) and U9 (Stack-Output, J5) - extra counts of the existing TPD4E05U06QDQARQ1 part - complete ESD coverage for ACTUATE_REQUEST signals on every live-swap connector. Stack-Output's J1/J2 REF_IN/REF_OUT and J5/J6 SIG-BLOCK-G/H wiring defined as passive passthrough (board has no active ICs). Found but NOT resolved: Stack-Blanking Board's design is inconsistent with the DEC-093 signal path (treats ACTUATE_REQUEST as a dead-end terminator rather than the actual reflection point) - raised separately for approval. |
| DEC-096 | Stack-Blanking Board Corrected: ENC_ACTIVE_N/ACTUATE_REQUEST_N Termination Removed; ACTUATE_REQUEST Bridging Added | 2026-09-02 | Decided | Removed stale R1 (ENC_ACTIVE_N pull-up, signal never routed here) and R5 (ACTUATE_REQUEST_N pull-up, obsolete dead-end model); remaining R2-R4 renumbered to R1-R3 (TCK/TMS/CPLD_RESET_N termination only). Added two new passive bridging paths for ACTUATE_REQUEST_OUT_N/REF_IN_N and ACTUATE_REQUEST_REF_OUT_N/IN_N, mirroring the existing ENC/TTD bridging pattern, since this board is the actual dual-reflection point for the round-trip actuation signal (DEC-093), not a terminator. |
| DEC-097 | Cypher J3 ACTUATE_REQUEST_OUT_N Wired to CPLD as Round-Trip Verification Input | 2026-09-02 | Decided | Pin 35 on Cypher's J3, previously NC, is now wired to CPLD U1 as a genuine input (self-test: verifies the ACTUATE_REQUEST round trip completed) plus new R51 (10kΩ pull-up to 3V3_ENIG) for idle-bias when disconnected (e.g. Stack-Blanking bench mode with no mini-stacks). Amends DEC-090's NC designation; pin position unchanged. |
| DEC-098 | Controller ↔ Cypher Dock Split: Power-Only Molex + Signal-Only Samtec (Amends DEC-038, DEC-080) | 2026-09-04 | Decided | Reallocates the Controller's former Stator dock (J4/J5) to the Cypher Board, split strictly by electrical function: J4 power-only (Molex, unchanged part numbers - 5x GND power-pitch, 8x 5V_MAIN + 7x 3V3_ENIG signal-pitch); J5 signal-only (new Samtec QSS/QTS-025 family, reusing existing qualified parts - USB D+/D-, I2C, reserved PWM/GPCLK). Removes the obsolete JTAG cluster from the dock entirely (JTAG bridge is native to Cypher). No TVS/ESD required (blind-mate dock). |
| DEC-099 | CM5 I2C Bank Architecture (I2C0 PM-Dedicated + I2C1-I2C6 via Cypher), MIPI0→MIPI1 Swap, PWM/GPCLK Reservation | 2026-09-04 | Decided | Expands from one shared I2C bus to six: I2C0 (PM-dedicated, GPIO8/9, via CTL J3) freed by AM retirement (DEC-100); I2C1 (existing active Cypher-peripherals bus, unchanged); I2C2/I2C3/I2C4/I2C6 reserved/NC on Cypher for a future Rotor-Cypher-Software-Updates discussion. Relocates ROTOR_EN_N/PM_IO_INT_N/USB_FAULT_N/PWR_GD to free GPIO for I2C2/I2C3. Moves Controller DSI1 (J9) from CM5 MIPI0 to MIPI1 to free I2C6's shared GPIO pair. Reserves 4x PWM0 + 2x GPCLK channels to bare test-pad loops on Cypher (TP1-TP12); flags DEC-022 buffering precedent for any future production use. |
| DEC-100 | JTAG Module and Actuation Module Retirement from Controller Board | 2026-09-04 | Decided | Removes the JM dock (J12, MH9-MH12) and AM host dock (J11, MH5-MH8, GPIO8 ACTUATE_REQUEST_N, R4 pull-up) from the Controller Board - both functions already consolidated elsewhere (JTAG bridge native to Cypher; Actuation Module MCU/solenoid circuitry native to Stack-Input, one instance per mini-stack, per DEC-093/DEC-097's round-trip chain). Frees GPIO8 for I2C0 (DEC-099). Full FR/DR/BOM renumbering on the Controller per project convention (DEC-055/DEC-080). Power_Budgets.md's "servo rail" line relocated (not removed) to reflect the solenoid's continued draw via its native Stack-Input instance. |
| DEC-101 | Cypher Board INA219 I2C Address Aligned to PM Default (0x45 → 0x40) | 2026-09-08 | Decided | Changes Cypher Board's INA219 (U2, rotor-stack telemetry) I2C address from 0x45 to 0x40, matching the Power Module's INA219 (U10) default address. Both now use the INA219's zero-strap default (A0/A1 to GND) - safe to duplicate since the two devices sit on independent I2C buses (I2C0 for PM, I2C1 for Cypher, per DEC-098/DEC-099). Simplifies both hardware (no address-strap components) and monitoring software (identical driver code, only the bus/bank differs). |
| DEC-102 | Cypher FT232H Moved to 3.3V VREGIN Self-Powered Operation (5V_USB Net Retired) | 2026-09-11 | Decided | FT232H (U17) moved to self-powered 3.3V VREGIN operation using the already-specified FT232HL-REEL's Rev C silicon capability - VREGIN and VCCD (an input in this mode, previously self-generated) both tied to 3V3_ENIG. Retires the 5V_USB net and its entry filter (C27) entirely - found to be a phantom/stale net left over from the pre-merge JTAG Daughterboard architecture, never actually present on the current Cypher/Controller dock (DEC-098). No 5V rail required anywhere in the USB-JTAG bridge. Closes jdb-ft232h-3v3-vregin. |
| DEC-103 | HID / USM Hub Connector Topology Rework | 2026-09-17 | Decided | Retires the HID boards' former right-pair J5/J7 chain-through connectors, adds a dedicated USM-facing right-edge connector on both HID boards, repurposes Cypher J6 as the USM hub, and repurposes Cypher-Plugboard J2 to mate USM rather than a HID board. |
| DEC-104 | User Settings Module Reworked as HID Colour / Audio Hub and JTAG/I2C Spine | 2026-09-17 | Decided | USM is now the shared HID lighting-colour / brightness hub, the placeholder audio board, and the JTAG / I2C spine between Cypher and the HID boards. CFG_ROUTE and panel-switch behaviour are removed from USM. |
| DEC-105 | CFG_ROUTE Moved to Full CM5 Software Control; Physical USM Switches Retired | 2026-09-17 | Decided | CFG_ROUTE[3:0] is now CM5-owned only. The physical USM switch and apply-button path is removed. CFG_REFMAP remains governed by DEC-089's JTAG UFM write decision. |
| DEC-106 | Cypher-Plugboard Reduced to Mechanical / Connector-Only Board | 2026-09-17 | Decided | Cypher-Plugboard now carries only the two board-to-board connectors and no active electrical components. The plugboard jack field remains mechanically mounted and harnessed directly to Cypher J20+. |
| DEC-107 | USM/HID Connector Four-Colour-Style Signal Expansion | 2026-09-21 | Decided | Template 3 (USM-to-HID connector) expanded from a single generic LED colour/brightness signal group to 4 independent colour-style groups, letting a HID board's own local logic access more than one stored colour value simultaneously. USM's colour-value store expands to 4 styles (3 used initially, 1 reserved). |