Electronics Cypher Design Spec - thepinkmile/Enigma-NG GitHub Wiki

Cypher Board (V1.0) Design Specification

Status: Draft Project: Enigma-NG Author: Izzyonstage & GitHub Copilot Version: v.0.1.0 Associated Hardware Revision: Rev A Last Updated: 2026-10-08

Diagrams

1. Overview

The Cypher Board is the central backplane of the Enigma-NG encryption engine. It fulfils the Stator and Reflector responsibilities of the historical Enigma machine within a single consolidated 6-layer PCB, and hosts the USB-JTAG programming bridge for the system.

Enigma Responsibility Board Role Key Component
Stator CPLD-based cipher routing, plugboard configuration, reflector map selection, I2C telemetry, power distribution to the rotor stack U1 — Intel MAX II EPM570T100I5N
Reflector Electrical turnaround at the end of the rotor stack; reflection mapping applied by CPLD U1 at Step 2 boundary J4 + U1 + R50
JTAG Bridge USB-to-JTAG programming for all 37 system CPLDs U17 — FT232H (MPSSE)

Rotor Mini-Stacks attach to the Cypher Board via keyed Samtec QSS-025 vertical female connectors (J3 and J4). Whichever HID board (Cypher-Input or Cypher-Output) is physically closest chains from J5 (Cypher Left Pair Template); the other HID board attaches further down the local stack via that board's own connectors. The User Settings Module connects via J6 (Hub Connector Template), relaying JTAG and the dedicated Cypher-peripherals I2C bus onward to both HID boards and to Cypher-Plugboard. The Controller Board connects via a split power/signal dock pair (Molex J1, power-only; Samtec J2, signal-only).

Functional Requirements

ID Functional Requirement Notes Satisfied By / Cross-Ref
FR-STA-01 Serve as the mechanical and electrical backplane for the 30-rotor stack Rotor positions distributed across Rotor Mini-Stacks (up to 6 mini-stacks = 30 positions) §2 Architecture; BOM J3, J4
FR-STA-02 Distribute 3V3_ENIG power to all 30 rotor positions simultaneously Via J3 and J4 power pins; 2oz copper pour; 4x ferrite beads L1–L4 §7 Power Telemetry; BOM L1–L4
FR-STA-03 Route the JTAG chain from the Controller Board through all 30 rotor positions in sequence Serial daisy-chain; CPLD U1 is device 7 (after the 4 Plugboard Encoder Modules); exits via J3 TTD pin §3 JTAG Hub; BOM U1
FR-STA-04 Receive TTD_RETURN from the end of the rotor chain and deliver it to the JTAG bridge Via J4 (Stack-Output/REF-side) → R50 → FT232H U17 TDO §4 Signal Turnaround; BOM J4, R50, U17
FR-STA-05 Interface with ENC modules for all cipher pipeline roles 4x back-face DF40C mounts for plugboard passes (J7–J18); J5 for HID (whichever of Cypher-Input/Cypher-Output is closest, either order) §6 Interconnects; BOM J5, J7–J18
FR-STA-06 Host a CPLD in the "static" portion of the system JTAG chain (after the 4 Plugboard Encoder Modules, before the Rotor stack) Intel MAX II EPM570T100I5N (570 LEs); device 7 of 37 §3 CPLD; BOM U1
FR-STA-07 Connect to the Controller Board via two docks split by electrical function J1 = power-only Molex dock (5V_MAIN, 3V3_ENIG, GND); J2 = signal-only Samtec dock (USB D+/D-, I2C, PWM/GPCLK reserved) §6 Interconnects; BOM J1, J2
FR-STA-08 Select the active plugboard routing configuration from the User Settings Module via I2C CFG_ROUTE[3:0] via U8 GPA[3:0]; 13 valid configurations (indices 0–12); indices 13–15 reserved §3 Configuration Bank 1; BOM U8
FR-STA-09 Select and apply a stored reflector substitution map at the reflection boundary CM5 writes the active map index directly into the CPLD via the existing JTAG chain (UFM in-system write) at configuration-apply time - no dedicated parallel GPIO bus; 21 pre-loaded maps §3 Configuration Bank 2; BOM U1
FR-STA-10 Provide I2C GPIO expansion for CM5 virtual keypress, HID monitoring, ENC service-bus monitoring, CPLD_RESET_N management, and CPLD configuration driving Three MCP23017 expanders U6, U7, U8 on I2C1 bus §3 I2C Devices; BOM U6–U8
FR-STA-11 Select between the physical keyboard source and CM5 virtual key source before the cipher pipeline 7-channel 2:1 mux (U4/U5); KEY_CM5_ACTIVE selects source §3 External Keyboard Source Mux; BOM U4, U5
FR-STA-12 Relay the dedicated Cypher-peripherals I2C bus and JTAG to the User Settings Module J6 = Hub Connector Template (owned by User_Settings_Module/Board_Layout.md §2); USM relays this bus and JTAG onward to both HID boards and to Cypher-Plugboard itself §6 Interconnects; BOM J6
FR-STA-13 Protect J3 (Stack-Input/STA-side) stacking connector from ESD during live mini-stack swap J3 carries JTAG + ENC + actuation-request signals; accessible during hot-swap §8 Thermal & ESD; BOM U9–U12, U19
FR-STA-14 Verify the ACTUATE_REQUEST round-trip signal completes correctly, as a system self-test CPLD U1 reads ACTUATE_REQUEST_OUT_N (J3 pin 35) and compares it against the originally-issued ACTUATE_REQUEST_IN_N §3 Actuation Request Chain; BOM R51
FR-REF-01 Terminate the JTAG daisy-chain at the end of the 30-rotor stack End-of-chain turnaround via J4 (Stack-Output/REF-side) §4 Signal Turnaround; BOM J4
FR-REF-02 Provide the reflection turnaround at the end of the rotor chain with the selected map applied Reflection mapping applied by CPLD U1 at Step 2 boundary; J4 provides the electrical return path §3 CPLD Signal Routing; BOM U1, J4
FR-REF-03 Return TTD_RETURN from the end of the chain to the JTAG bridge J4 → R50 (22 Ohm) → FT232H U17 TDO §4 Signal Turnaround; BOM R50, U17
FR-REF-04 Provide end-of-chain JTAG signal damping R50 = 22 Ohm 0603 series resistor on TTD_RETURN §4 Signal Turnaround; BOM R50
FR-REF-05 Protect J4 (Stack-Output/REF-side) stacking connector from ESD during live mini-stack swap J4 carries TTD_RETURN + ENC return signals; accessible during hot-swap §8 Thermal & ESD; BOM U13–U16
FR-CYP-01 Provide USB-to-JTAG bridge for programming all 37 CPLDs in the system FT232H in MPSSE mode, self-powered from 3V3_ENIG; USB D+/D- via CTL signal dock J2 to CM5 §5 USB-JTAG Bridge; BOM U17, U18, Y1
FR-CYP-02 Interface with up to 6 Rotor Mini-Stacks via keyed stacking connectors J3 = Stack-Input/STA-side; J4 = Stack-Output/REF-side §6 Interconnects; BOM J3, J4
FR-CYP-03 Interface with whichever HID board (Cypher-Input or Cypher-Output) is physically closest J5 = Cypher Left Pair Template (the other HID board attaches further down the local stack via that board's own connectors, not directly to this board); see Board_Layout.md §4 §6 Interconnects; BOM J5
FR-CYP-03a Interface with the User Settings Module as the JTAG/I2C spine hub J6 = Hub Connector Template, mates USM's own top connector; see Board_Layout.md §5 §6 Interconnects; BOM J6
FR-CYP-04 Host 4 ENC module mounts on the back face for plugboard-role encoder modules DF40C Hirose BtB receptacle sets §6 Interconnects; BOM J7–J18
FR-CYP-05 Carry spade blade terminal bank on the back face for jack plug harnesses Keystone 1285-ST; 64 per ENC mount position × 4 = 256 total §6 Interconnects; BOM J20+
FR-CYP-06 Provide bare test-pad access to reserved CM5 PWM and GPCLK channels for future peripheral use 4x PWM0 channels + GPCLK[0]/GPCLK[1] from CTL signal dock J2, terminated at bare test-pad loops (no active devices populated) §6 Interconnects; BOM TP1-TP12

Design Requirements

ID Design Requirement Specification Satisfied By / Cross-Ref
DR-STA-01 PCB stackup 6-layer / 2oz copper per design/Standards/Global_Routing_Spec.md §2.3.4 §9 PCB Fabrication & Stackup
DR-STA-02 Layer mapping L1 Signal/front face, L2 GND, L3 Inner signal (CI), L4 Power, L5 GND, L6 Signal/back face — per design/Standards/Global_Routing_Spec.md §2.3.4 §9 PCB Fabrication & Stackup
DR-STA-03 Stack-Input / STA-side rotor interface J3 = QSS-025-01-L-D-A-GP-K (50-contact vertical female); pin mapping owned by Stack-Input/Board_Layout.md §1 (IC-STA-CHAIN, DEC-094) §6 Interconnects; BOM J3
DR-STA-04 ENC module and HID board interface J5 = QSS-025-01-L-D-A-GP-K (Cypher Left Pair Template, vertical female - mates whichever of Cypher-Input/Cypher-Output is closest, either order); J7–J18 = DF40C-xDS sets (4x plugboard passes) §6 Interconnects; BOM J5, J7–J18
DR-STA-06 Controller dock connectors J1 = Molex 2195620015 (power-only plug: 5x GND power-pitch, 8x 5V_MAIN + 7x 3V3_ENIG signal-pitch); J2 = Samtec QTS-025-01-L-D-RA-P (signal-only plug: USB D+/D-, I2C, PWM/GPCLK reserved); mating CTL receptacles = Molex 2195630015 (J1) / Samtec QSS-025-01-L-D-A-GP-K (J2). See DEC-098. §6 Interconnects; BOM J1, J2
DR-STA-07 CPLD Intel MAX II EPM570T100I5N (TQFP-100); 570 LEs; same footprint as EPM240; 570 LEs required for startup-loaded 64-char reflector map (384 FFs) + routing matrix logic §3 CPLD; BOM U1
DR-STA-08 Power monitoring INA219 current sensor (U2); shunt R1 = KRL6432T4-M-R010-F-T1 (10 mOhm 6432/2512 Kelvin 4-terminal) §7 Power Telemetry; BOM U2, R1
DR-STA-09 Maximum 3V3_ENIG load 2.05 A worst-case typical (30 rotors + CPLD + all encoders) §7 Power Telemetry
DR-STA-10 Routing configuration selection CFG_ROUTE[3:0] driven by U8 GPA[3:0]; 4x 10 kOhm pull-down R13–R16 on CPLD inputs (power-up safe default = 0) §3 Configuration Bank 1; BOM U8, R13–R16
DR-STA-11 Reflector map selection Active map index written directly into the CPLD's UFM via the existing JTAG chain at CM5 configuration-apply time - see §3 Configuration Bank 2. No dedicated parallel input pins or pull-down resistors required §3 Configuration Bank 2; BOM U1
DR-STA-12 I2C GPIO expanders U6 = MCP23017T-E/SO @ 0x20; U7 = MCP23017T-E/SO @ 0x21; U8 = MCP23017T-E/SO @ 0x22; SOIC-28; dedicated /RESET pull-ups R36 (U6), R37 (U7), R38 (U8) — 10 kOhm each to 3V3_ENIG BOM U6–U8, R36–R38
DR-STA-13 U8 specification U8 = MCP23017T-E/SO; SOIC-28; A2=LOW, A1=HIGH, A0=LOW; GPA[3:0] = CFG_ROUTE[3:0]; GPA[6] = CFG_APPLY_N; GPB[5:0] not connected BOM U8
DR-STA-14 USM Hub connector J6 = QSS-025-01-L-D-A-GP-K (vertical female), Hub Connector Template (owned by User_Settings_Module/Board_Layout.md §2); carries 3V3_ENIG, the dedicated Cypher-peripherals I2C bus, and JTAG §6 Interconnects; BOM J6
DR-STA-15 CFG_APPLY_N signal CFG_APPLY_N = active-low Stator-only reload pulse from U8 GPA[6]; ANDed with CPLD_RESET_N through U3 (SN74LVC1G08DBVR) to drive CPLD DEV_CLR_N; R17 (10 kOhm pull-up to 3V3_ENIG) holds CFG_APPLY_N deasserted at power-up BOM U8, U3, R17
DR-STA-16 ESD protection — J3 Stack-Input/STA-side U9 (JTAG: TTD, TMS, TCK, CPLD_RESET_N) + U10–U12 (ENC: ENC_IN[5:0] + ENC_OUT[5:0]) + U19 (ACTUATE_REQUEST_IN_N/OUT_N); placed within 3mm of J3 mating edge §8 Thermal & ESD; BOM U9–U12, U19
DR-STA-17 Mounting holes MH1–MH4: M3 PTH (3.2 mm drill) tied to GND_CHASSIS per GRS §4; placement per GRS §4.3 (pattern TBD — board shape TBD). No BOM entry. §9 PCB Fabrication; GRS §4.3
DR-STA-18 CPLD_RESET_N open-drain buffer Q1 = BSS138 N-ch MOSFET SOT-23; gate resistor R41 = 100 Ohm 0402; driven by U7 GPA[7]; prevents MCP23017 IOL overload from 30-rotor pull-up stack (30 x 330 uA = 9.90 mA > 8 mA I/O sink limit) BOM Q1, R41
DR-STA-19 ACTUATE_REQUEST_OUT_N idle-bias / round-trip readback R51 = 10 kOhm 0402 pull-up to 3V3_ENIG on J3 pin 35, in addition to the CPLD U1 input connection; defines the idle state when disconnected (e.g. Stack-Blanking Board bench mode with no mini-stacks attached) and allows U1 firmware to verify the ACTUATE_REQUEST round trip completed. Per DEC-097. §3 Actuation Request Chain; BOM R51
DR-REF-02 Stack-Output / REF-side interface J4 = QSS-025-01-L-D-A-GP-K (50-contact vertical female); pin mapping owned by Stack-Output/Board_Layout.md §1 (IC-REF-CHAIN, DEC-094) §6 Interconnects; BOM J4
DR-REF-03 TTD_RETURN routing TTD_RETURN received on J4 from Stack-Output; routed via R50 (22 Ohm) to FT232H U17 TDO §4 Signal Turnaround; BOM J4, R50
DR-REF-04 End-of-chain damping R50 = 22 Ohm, 0603, ERJ-3EKF2200V, on TTD_RETURN from J4 to U17 TDO §4 Signal Turnaround; BOM R50
DR-REF-05 Reflection mapping Reflection mapping handled by CPLD U1 at Step 2 boundary; no passive turnaround traces required §3 CPLD Signal Routing
DR-REF-06 ESD protection — J4 Stack-Output/REF-side U13–U16 (TPD4E05U06QDQARQ1 x4); placed within 3mm of J4 mating edge §8 Thermal & ESD; BOM U13–U16
DR-CYP-01 PCB stackup 6-layer / 2oz copper per design/Standards/Global_Routing_Spec.md §2.3.4; PCBWay prototype manufacturer §9 PCB Fabrication & Stackup
DR-CYP-02 Prototype manufacturer PCBWay (JLCPCB not suitable for 6-layer + double-sided assembly) §9 PCB Fabrication & Stackup
DR-CYP-03 Stack-Input stacking connector J3 = QSS-025-01-L-D-A-GP-K (Samtec 50-contact 0.635mm vertical female SMT) §6 Interconnects; BOM J3
DR-CYP-04 Stack-Output stacking connector J4 = QSS-025-01-L-D-A-GP-K (Samtec 50-contact 0.635mm vertical female SMT) §6 Interconnects; BOM J4
DR-CYP-05 Cypher-Input/Cypher-Output connector J5 = QSS-025-01-L-D-A-GP-K (Samtec 50-contact 0.635mm vertical female SMT); Cypher Left Pair Template (owned by this board) - carries 3V3_ENIG/5V_MAIN/GND, ENC_DATA_IN[5:0]/ENC_DATA_OUT[5:0], ENC_ACTIVE_INPUT_N/ENC_ACTIVE_OUTPUT_N, and BOARD_ROLE_ID_IN[3:0]/BOARD_ROLE_ID_OUT[3:0]; mates whichever HID board's top (right-angle male, QTS-025-01-L-D-RA-P) connector is closest — either order supported; pin mapping Board_Layout.md §4 §6 Interconnects; BOM J5
DR-CYP-05a User Settings Module connector J6 = QSS-025-01-L-D-A-GP-K (Samtec 50-contact 0.635mm vertical female SMT); mates USM's own top (right-angle male, QTS-025-01-L-D-RA-P) Hub connector; pin-level template owned by User_Settings_Module/Board_Layout.md §2 §6 Interconnects; BOM J6
DR-CYP-06 ENC module mounts (x4 on back face) J7–J9, J10–J12, J13–J15, J16–J18 = DF40C-90DS + DF40C-24DS + DF40C-10DS per mount (Hirose 0.4mm pitch) §6 Interconnects; BOM J7–J18
DR-CYP-07 Spade blade terminal bank on back face Keystone 1285-ST (6.35mm PCB vertical THT); 64 per ENC mount position x 4 = 256 total; RefDes J20+ (arrangement TBD at schematic time) §6 Interconnects; BOM J20+
DR-CYP-08 USB-JTAG bridge U17 = FT232HL-REEL LQFP-48 (MPSSE mode; Rev C silicon, self-powered from 3V3_ENIG via VREGIN — see DR-CYP-11); U18 = SN74LVC2G125DCUR VSSOP-8; Y1 = 435F12012IET 12MHz SMD-5032 §5 USB-JTAG Bridge; BOM U17, U18, Y1
DR-CYP-09 Controller dock split by electrical function J1 (power-only Molex) carries zero signal contacts; J2 (signal-only Samtec) carries zero power rails. See DEC-098. §6 Interconnects; BOM J1, J2
DR-CYP-10 PWM/GPCLK test pads TP1-TP6 = bare copper test-pad loops for PWM0[0-3] + GPCLK[0]/GPCLK[1] (one per signal, received from CTL J2); TP7-TP12 = paired GND test-pad loops, one adjacent to each signal pad. No BOM entry (bare copper feature, no component). No active devices populated at this time; any future use requires local buffering per DEC-022 precedent. See DEC-099. §6 Interconnects; Board_Layout.md §1
DR-CYP-11 FT232H 3.3V VREGIN self-powered architecture U17 (FT232HL-REEL, Rev C silicon) powered entirely from 3V3_ENIG: VREGIN (pin 40) and VCCD (pin 39, an input) both tied to 3V3_ENIG, alongside the existing VCCIO/VPLL/VPHY connections. No 5V rail required anywhere in the USB-JTAG bridge. See DEC-102. §5 USB-JTAG Bridge; BOM U17

Component Block Diagram

flowchart TD
  subgraph ctrlIface["Controller Interface"]
    J1["J1 Molex 2195620015\nPower-Only Dock (5V_MAIN / 3V3_ENIG / GND)"]
    J2["J2 Samtec QTS-025-01-L-D-RA-P\nSignal-Only Dock (USB D+/D- / I2C / PWM / GPCLK)"]
  end

  subgraph jtagBridge["USB-JTAG Bridge"]
    U17["U17 FT232H LQFP-48\n(MPSSE mode)"]
    U18["U18 SN74LVC2G125\nJTAG Buffer (TCK/TMS)"]
    Y1["Y1 435F12012IET\n12 MHz Crystal"]
  end

  subgraph cpldCore["CPLD Signal Router (Stator Responsibility)"]
    U1["U1 EPM570T100I5N\nRouting / Reflection / Config"]
    U2["U2 INA219\nCurrent Monitor"]
    U3["U3 SN74LVC1G08\nAND Gate"]
    U4U5["U4 U5 74HC157 MUX x2\nKeyboard Source Select"]
    U6U8["U6 U7 U8 MCP23017 x3\nI2C Expanders"]
    Q1["Q1 BSS138\nCPLD_RESET_N Open-Drain Buffer"]
  end

  subgraph stackIface["Mini-Stack Interface"]
    J3["J3 QSS-025 female\nStack-Input / STA side"]
    J4["J4 QSS-025 female\nStack-Output / REF side"]
    U9U12["U9-U12 TPD4E05 x4 ESD\nJ3 protection"]
    U19["U19 TPD4E05 ESD\nJ3 ACTUATE_REQUEST_IN/OUT_N"]
    R51["R51 10kΩ pull-up\nACTUATE_REQUEST_OUT_N idle-bias"]
    U13U16["U13-U16 TPD4E05 x4 ESD\nJ4 protection"]
  end

  subgraph ioCypher["Cypher-Input / Cypher-Output Interface"]
    J5["J5 QSS-025 female\nCypher Left Pair Template\n(whichever HID board is closest)"]
  end

  subgraph usmIface["User Settings Module Interface"]
    J6["J6 QSS-025 female\nHub Connector Template\n(JTAG + Cypher-peripherals I2C)"]
  end

  subgraph encMounts["ENC Module Mounts — back face"]
    J7J9["J7-J9 DF40C\nMount 1 — PLG_PASS1_DEC"]
    J10J12["J10-J12 DF40C\nMount 2 — PLG_PASS1_ENC"]
    J13J15["J13-J15 DF40C\nMount 3 — PLG_PASS2_DEC"]
    J16J18["J16-J18 DF40C\nMount 4 — PLG_PASS2_ENC"]
  end

  J1 -- "3V3_ENIG (VREGIN + VCCD) to FT232H" --> U17
  J1 -- "3V3_ENIG" --> U1
  J2 -- "USB D+/D- to CM5" --> U17
  J2 -- "I2C1 bus" --> U6U8
  J2 -- "I2C1 bus" --> U2
  U17 -- "TDI (chain entry)" --> J6
  J6 -- "HID sub-chain TDO (chain continues)" --> J7J9
  U18 -- "TCK / TMS buffered" --> U1
  U3 --> U1
  U6U8 -- "CPLD_RESET_N" --> Q1
  Q1 -- "open-drain" --> U3
  U1 -- "JTAG out + ENC" --> J3
  J3 -- "ACTUATE_REQUEST_OUT_N (round-trip check)" --> U1
  J3 --> R51
  J4 -- "TTD_RETURN + ENC return" --> U1
  U1 <--> J5
  U1 <--> J7J9
  U1 <--> J10J12
  U1 <--> J13J15
  U1 <--> J16J18
  U9U12 --> J3
  U19 --> J3
  U13U16 --> J4

2. Architecture

  • PCB: 6-layer / 2oz copper. ENIG Gold. 2.0mm filleted corners.
  • Prototype manufacturer: PCBWay (JLCPCB not suitable for 6-layer + double-sided assembly).
  • Data plate: inverted white data plate on bottom layer.

GND_CHASSIS Single-Point Bond

Per design/Standards/Global_Routing_Spec.md §5: the Cypher Board implements a local GND_CHASSIS net tied to its mounting holes and any deliberate enclosure-contact features, but does not implement a local GND to GND_CHASSIS bond. The system's only galvanic GND to GND_CHASSIS bond remains on the Power Module at the common power-entry point immediately before the eFuse.

3. CPLD Signal Routing (Stator Responsibility)

CPLD: Intel MAX II EPM570T100I5N (U1, TQFP-100). 570 LEs.

Port Mapping

The Cypher Board's external cipher pipeline interfaces. Original Stator port group names are carried forward in parentheses for schematic capture continuity.

Cypher Connector Stator Port Group CPLD Role
J5 QSS-025 (Cypher Left Pair Template) top row KBD_ENC Keyboard encode source — Forward entry Step 1 (whichever HID board is closest relays this row from Cypher-Input)
J5 QSS-025 (Cypher Left Pair Template) bottom row LBD_DEC Lightboard decode destination — Final exit Step 3 (relayed onward to Cypher-Output)
J7–J9 DF40C Mount 1 PLG_PASS1_DEC Plugboard Pass 1 decode
J10–J12 DF40C Mount 2 PLG_PASS1_ENC Plugboard Pass 1 encode
J13–J15 DF40C Mount 3 PLG_PASS2_DEC Plugboard Pass 2 decode
J16–J18 DF40C Mount 4 PLG_PASS2_ENC Plugboard Pass 2 encode
J3 QSS-025 (Stack-Input/STA-side) Mini-Stack 1 Rotor 1 JTAG + ENC forward into first mini-stack
J4 QSS-025 (Stack-Output/REF-side) Reflection Interconnect TTD_RETURN + ENC reflection return
J6 QSS-025 (Hub Connector Template) USM Spine JTAG + Cypher-peripherals I2C relay to/from the User Settings Module

CPLD Signal Routing Matrix

The CPLD (U1) is the bidirectional ENC_DATA routing hub for the full encryption cycle.

Fixed interfaces:

  • J5 top row (ENC_DATA_IN[5:0]/ENC_ACTIVE_INPUT_N) — KBD_ENC keyboard encode source, originating at Cypher-Input, relayed through whichever HID board is closest if that is Cypher-Output
  • J5 bottom row (ENC_DATA_OUT[5:0]/ENC_ACTIVE_OUTPUT_N) — LBD_DEC lightboard decode destination, generated by this board (see ENC_ACTIVE_N note below) and relayed onward to Cypher-Output
  • J3 — Mini-Stack 1 Rotor 1 connector (Stack-Input/STA-side stacking connector)
  • J4 — Reflection Interconnect connector (Stack-Output/REF-side stacking connector)

Configurable plugboard passes:

  • J7–J9 / J10–J12 = Plugboard Pass 1 (DEC/ENC DF40C mounts, back face)
  • J13–J15 / J16–J18 = Plugboard Pass 2 (DEC/ENC DF40C mounts, back face)

The encryption signal passes through U1 at three defined interception points:

Step CPLD receives from Optional plugboard insertion CPLD drives to
1 — Forward entry J5 top row ENC_DATA_IN[5:0] — keyboard keystroke Pre-Rotor 1: Pass 1 and/or Pass 2 J3 ENC_OUT_ROT[5:0] → Rotor 1 (forward pass through rotor stack)
2 — Reflector return J4 ENC_IN_REF[5:0] — reflected signal from Stack-Output At Reflector boundary: Pass 1 and/or Pass 2 J4 ENC_OUT_REF[5:0] → Stack-Output → Rotor 30 (return pass through rotor stack)
3 — Final exit J3 ENC_IN_ROT[5:0] — Rotor 1 return-pass output Post-Rotor 1 return: Pass 1 and/or Pass 2 J5 bottom row ENC_DATA_OUT[5:0] → Cypher-Output (lightboard)

ENC_ACTIVE_N is a HID-local sideband only. Cypher-Input generates its own ENC_ACTIVE_INPUT_N on J5's top row, which terminates at this board only (never tapped or relayed further by any intermediate HID board). This board's own CPLD firmware accounts for the cipher pipeline's propagation delay and then generates a separate ENC_ACTIVE_OUTPUT_N signal on J5's bottom row, for Cypher-Output to consume - Cypher-Output is ENC_ACTIVE_OUTPUT_N's legitimate destination, not an intermediate relay of Cypher-Input's own signal. Neither signal is propagated through the plugboard, rotor, or reflector interfaces.

Actuation Request Chain (J3 / J4)

ACTUATE_REQUEST_IN_N/ACTUATE_REQUEST_OUT_N (on J3) and ACTUATE_REQUEST_REF_IN_N/ ACTUATE_REQUEST_REF_OUT_N (on J4) together form a single round-trip signal path that triggers rotor-stepping actuation across the entire 30-rotor stack once per keypress. Full path (see DEC-093 for complete detail and per-board wiring):

  1. Origination: CPLD U1 asserts ACTUATE_REQUEST_IN_N on J3 (pin 16) based on ENC_ACTIVE_N (received from Cypher-Input, indicating a key is actively depressed) combined with U1's own firmware configuration — this is the only place the actuation trigger is gated on keypress state (see DEC-091).
  2. Forward pass (STA chain): the signal propagates through every Rotor Mini-Stack's Stack-Input → Rotor 1-5 → Stack-Output → Stack-Interposer → back to that same mini-stack's own Stack-Input rear connector → next mini-stack's front connector, repeating until it reaches the Stack-Blanking Board.
  3. First reflection (Blanking → Cypher, REF chain): the Stack-Blanking Board redirects the signal into the REF-side chain (Stack-Output boards only, direct passthrough, no rotors involved), propagating it back through every mini-stack to Cypher's J4, arriving as ACTUATE_REQUEST_REF_IN_N (pin 16).
  4. CPLD reflection: U1's firmware processes ACTUATE_REQUEST_REF_IN_N and drives ACTUATE_REQUEST_REF_OUT_N (pin 35) in response.
  5. Second forward pass (REF chain): ACTUATE_REQUEST_REF_OUT_N propagates forward again through the Stack-Output boards of every mini-stack back to the Stack-Blanking Board.
  6. Second reflection (Blanking → Cypher, STA chain, reverse rotor order): the Stack-Blanking Board redirects the signal back into the STA-side chain, entering at the last mini-stack's Stack-Input rear connector this time, traversing the Stack-Interposer/Stack-Output/Rotor chain in reverse (right-to-left, i.e. each Rotor's own IN-to-OUT pins used the opposite way round from the forward pass), back through every mini-stack to Mini-Stack 1's Stack-Input front connector, and finally to Cypher's J3 ACTUATE_REQUEST_OUT_N (pin 35), where CPLD U1 reads it as a round-trip completion check against the originally-issued ACTUATE_REQUEST_IN_N (per DEC-097).

This mirrors the existing four-pass structure already used for the ENC_DATA/cipher signal itself (forward via J3/rotors, reflect at Blanking, back via J4, CPLD reflection-map processing, forward via J4 again, reflect at Blanking again, back via J3/rotors in reverse) — see §3 CPLD Signal Routing Matrix above.

Every downstream Rotor Mini-Stack / Rotor board carries all four related nets (front-IN, front-OUT, rear-IN, rear-OUT, per DEC-090's board-agnostic model), with each board's own CPLD (or, for the Stack-Input Board, its native STM32G071 AM controller) using its own dynamic configuration to decide how a given pass is actually routed. See DEC-090, DEC-093.

Configuration Bank 1 — Plugboard Routing

User Settings Module toggle switches provide a 4-bit user-intent image of CFG_ROUTE[3:0], selecting one of 13 valid routing configurations synthesised into the CPLD fabric as a case statement. Final CFG_ROUTE[3:0] driven by U8 GPA[3:0] via I2C. Pull-down R13–R16 (10 kOhm) hold CPLD inputs at logic-0 when U8 uninitialised (power-up safe default = config 0, no plugboard).

Plugboard Insertion Rules (for CPLD synthesis validation)

  1. Three insertion positions exist in the cipher pipeline: Pre-Rotor 1, At Reflector, and Post-Rotor 1 Return.
  2. Each insertion position may hold at most one plugboard pass per configuration.
  3. Each plugboard pass (Pass 1 or Pass 2) may be assigned to at most one position per configuration, or left uninserted (None).
  4. Any configuration where Pass 1 and Pass 2 occupy the same non-None position is invalid and must not be synthesised. Three such states exist (indices 13–15 are reserved for this reason).
  5. The CPLD when others clause shall produce the same behaviour as config 0 (no insertion) for all reserved indices.
CFG_ROUTE Pass 1 (J7–J12) Pass 2 (J13–J18) Notes
0 (0000) None None No plugboard — straight cipher pass
1 (0001) Pre-Rotor 1 Post-Rotor 1 Return Classic Enigma (Steckerbrett) — symmetric at keyboard entry and lightboard exit
2 (0010) At Reflector None Later Enigma variants — single pass at reflection boundary
3 (0011) Pre-Rotor 1 None Single pass — forward entry only
4 (0100) Post-Rotor 1 Return None Single pass — return exit only
5 (0101) None Pre-Rotor 1 Single pass — forward entry (Pass 2 module)
6 (0110) None At Reflector Single pass — reflection boundary (Pass 2 module)
7 (0111) None Post-Rotor 1 Return Single pass — return exit (Pass 2 module)
8 (1000) Pre-Rotor 1 At Reflector Dual pass — forward entry + reflection boundary
9 (1001) At Reflector Pre-Rotor 1 Dual pass — reflection boundary + forward entry
10 (1010) At Reflector Post-Rotor 1 Return Dual pass — reflection boundary + return exit
11 (1011) Post-Rotor 1 Return Pre-Rotor 1 Dual pass — return exit + forward entry
12 (1100) Post-Rotor 1 Return At Reflector Dual pass — return exit + reflection boundary
13–15 Reserved — Unused; CPLD shall treat as config 0

Configuration Bank 2 — Reflector Mapping

CM5 selects the active reflector map by writing the desired map index directly into the CPLD's UFM via the existing JTAG chain (in-system UFM write, using the same FT232H JTAG bridge already used for full CPLD programming) at configuration-apply time - no parallel GPIO bus or pull-down resistors are required. See User_Settings_Module/Design_Spec.md §1 for the User Settings Module's own front-panel hardware. This mechanism's CPLD I/O headroom (see CPLD I/O Budget below) is used for the Cypher-Input/Cypher-Output BOARD_ROLE_ID compatibility comparator (see §3a).

The Stack-Output/REF-side connection (J4) remains mandatory and provides the physical electrical return path; Bank 2 selects which involutory map U1 applies at the Step 2 reflection boundary. R17 (10 kOhm pull-up to 3V3_ENIG) holds CFG_APPLY_N deasserted at power-up.

UFM map storage: 21 involutory reflector maps; 64-entry x 6-bit format (384 bits per map; 21 x 384 = 8,064 bits <= 8,192-bit UFM).

Index Map Notes
0 UKW-A equivalent Historical Enigma Reflector A (26-char; entries 26–63 = identity for 64-char variant)
1 UKW-B equivalent Most common WWII Enigma variant
2 UKW-C equivalent Later wartime variant
3–20 Custom Available for user-defined involutory maps via JTAG programming

EPM570T100I5N Power Rail Assignments

Domain Pin count (TQFP-100) Connected to Bypass caps
VCCINT (core supply, 3.3V MultiVolt) 8 3V3_ENIG C1–C8 (100nF 0402 x8, one per pin)
VCCIO (I/O supply, 3.3V) 8 3V3_ENIG C14–C21 (100nF 0402 x8, one per pin)

All bypass capacitors placed within 1mm of their respective supply pin per GRS §3.2.

CPLD I/O Budget

The EPM570T100I5N TQFP-100 provides 76 user I/O pins. Dedicated pins (TCK, TMS, TDI, TDO, DEV_CLR_N) are not part of the user I/O budget.

Signal Group Count Direction
J3 Stack-Input/STA-side — ENC_OUT_ROT[5:0] 6 Output
J3 Stack-Input/STA-side — ENC_IN_ROT[5:0] 6 Input
J5 top row KBD_ENC — ENC_DATA_IN[5:0] 6 Input
J5 bottom row LBD_DEC — ENC_DATA_OUT[5:0] 6 Output
J7–J9 PLG_PASS1_DEC — decode output 6 Output
J10–J12 PLG_PASS1_ENC — encode input 6 Input
J13–J15 PLG_PASS2_DEC — decode output 6 Output
J16–J18 PLG_PASS2_ENC — encode input 6 Input
J4 Stack-Output/REF-side — ENC_OUT_REF[5:0] 6 Output
J4 Stack-Output/REF-side — ENC_IN_REF[5:0] 6 Input
ENC routing subtotal 60 —
U8 routing config input — CFG_ROUTE[3:0] 4 Input
BOARD_ROLE_ID_IN[3:0] — Cypher-Input capability ID (from J5 top row) 4 Input
BOARD_ROLE_ID_OUT[3:0] — Cypher-Output capability ID (from J5 bottom row) 4 Input
HID_VARIANT_ID[3:0] — resolved compatibility result to U7 GPIO expander 4 Output
Config subtotal 16 —
Total user I/O 76 / 76 —

CFG_REFMAP[5:0] is not used - the reflector map is selected via a JTAG UFM write instead (see Configuration Bank 2 above). BOARD_ROLE_ID_IN[3:0], BOARD_ROLE_ID_OUT[3:0], and HID_VARIANT_ID[3:0] occupy the resulting CPLD I/O. All 76 user I/O pins are allocated.

ENC_ACTIVE_N sidebands handled by external mux (U4/U5) and routed through U7 MCP23017 GPIO; not counted in CPLD user I/O budget.

§3a BOARD_ROLE_ID Compatibility Comparator

The Cypher Board's own CPLD (U1) receives both HID boards' BOARD_ROLE_ID[3:0] capability values directly - J5's top row always carries the Cypher-Input board's own ID (BOARD_ROLE_ID_IN[3:0]) and the bottom row always carries the Cypher-Output board's own ID (BOARD_ROLE_ID_OUT[3:0]), per each board's own fixed passthrough wiring convention (regardless of which physical HID board occupies the position closest to the Cypher Board) - see Board_Layout.md §4.

Capability bit definition (shared meaning on both Input and Output IDs):

Bit Meaning
0 Characters (A-Z letters)
1 Numbers (0-9 digits)
2 Special (symbols, e.g. base64-extra +//)
3 Custom (board declares support for a non-standard capability combination)

Known variant values:

Variant Value Notes
26-Char Classic 0b0001 Characters only
10-Numeric 0b0010 Numbers only
64-Character (default) 0b0111 Characters + Numbers + Special
64-Character (custom-support enabled) 0b1111 As above, plus Custom bit asserted via a user-accessible SPDT switch (Cypher-Output only - see Cypher-Output/Design_Spec.md once created)
Fully custom board Any other 4-bit combination Not an enumerated index - any bit combination not matching a defined variant is valid for a genuinely custom board's own capability declaration

Compatibility rule: Cypher-Output is compatible with Cypher-Input if and only if every capability bit set in the Input's ID is also set in the Output's ID - i.e. AND(BOARD_ROLE_ID_OUT, BOARD_ROLE_ID_IN) == BOARD_ROLE_ID_IN (the Output's capabilities are a superset of the Input's requirements). This single AND-based rule also correctly handles the Custom bit with no special-casing: an Input with Custom set (bit 3 = 1) only matches an Output that also has Custom asserted (e.g. the 64-Character Output's user-accessible switch bridged to "on").

Output: HID_VARIANT_ID[3:0] = BOARD_ROLE_ID_IN[3:0] (mirrors the Input's own ID) when compatible, or 0b0000 (the error/incompatible sentinel - not a valid ID for any real keyboard, since a real board always asserts at least one capability bit) when the compatibility rule fails. This drives an input pin bank on U7 (I2C GPIO expander, GPB[5:2]) for CM5 visibility.

External Keyboard Source Mux

7-channel 2:1 mux using U4 and U5 (74HC157PW-Q100,118) at the J5 top-row KBD_ENC entry point:

  • KEY_CM5_ACTIVE=0 (default): physical keyboard bundle forwarded — ENC_IN_KBD[5:0] + ENC_ACTIVE_INPUT_N
  • KEY_CM5_ACTIVE=1: CM5 virtual-key bundle forwarded — CM5_KEY_DATA[5:0] + CM5_KEY_ACTIVE_N

Both E pins of U4/U5 tied to GND; mux path always enabled when board is powered. Selected activity state, after this board's own CPLD firmware accounts for the cipher pipeline's propagation delay, is driven onto J5's bottom row as ENC_ACTIVE_OUTPUT_N (a signal this board generates, not merely forwards - see §3 CPLD Signal Routing Matrix) so Cypher-Output can blank when no key event is active, and is also monitored through U7 for GUI / telemetry visibility.

Device-to-Design Net Name Mapping

Component Pin Name Design Net Name Notes
/RESET (MCP23017 pin 9, U6/U7/U8) — (chip-local) Active-low chip reset; held HIGH via R36/R37/R38 (10 kOhm each to 3V3_ENIG); NOT connected to CPLD_RESET_N
DEV_CLR_N (EPM570T100I5N U1) AND(CPLD_RESET_N, CFG_APPLY_N) Driven by AND gate U3; either signal asserted LOW clears CPLD routing matrix. GRS §10 name: DEV_CLR_N.
TDI (EPM570T100I5N U1) TTD (inbound from Mount4 TDO, DF40C Connector B) Incoming JTAG serial data; U1 is device 7 in the chain, after the 4 Plugboard Encoder Modules
TDO (EPM570T100I5N U1) TTD (outbound to J3 TTD pin) CPLD TDO exits to the Stack-Input/STA-side connector, continuing into the Rotor mini-stack chain

I2C1 Bus Devices

Device Ref I2C Address Function
MCP23017 U6 0x20 ENC service-bus monitoring
MCP23017 U7 0x21 CM5 virtual-key injection; CPLD_RESET_N output; activity monitoring
MCP23017 U8 0x22 CPLD configuration driver (CFG_ROUTE + CFG_APPLY_N); GPB[5:0] not connected
INA219 U2 See Controller/Design_Spec.md §4.1 Rotor stack current/power telemetry

U6 — MCP23017T-E/SO @ 0x20

Monitors the HID cipher path. All active pins are inputs.

Address: 0x20 — A2=LOW, A1=LOW, A0=LOW

Port Pin Signal Direction Notes
GPA [0] ENC_IN[0] Bidirectional(Input) Monitor: cipher input bit 0 — post keyboard-source mux, forward path to CPLD
GPA [1] ENC_IN[1] Bidirectional(Input) Monitor: cipher input bit 1
GPA [2] ENC_IN[2] Bidirectional(Input) Monitor: cipher input bit 2
GPA [3] ENC_IN[3] Bidirectional(Input) Monitor: cipher input bit 3
GPA [4] ENC_IN[4] Bidirectional(Input) Monitor: cipher input bit 4
GPA [5] ENC_IN[5] Bidirectional(Input) Monitor: cipher input bit 5
GPA [6] ENC_ACTIVE_INPUT_N Bidirectional(Input) Monitor: selected keyboard-source activity sideband (active-LOW)
GPA [7] NC Output MCP23017 silicon restriction: GPA[7] output-only (DS20001952D §1); NC
GPB [0] ENC_OUT[0] Bidirectional(Input) Monitor: cipher output bit 0 — CPLD return path to Cypher-Output
GPB [1] ENC_OUT[1] Bidirectional(Input) Monitor: cipher output bit 1
GPB [2] ENC_OUT[2] Bidirectional(Input) Monitor: cipher output bit 2
GPB [3] ENC_OUT[3] Bidirectional(Input) Monitor: cipher output bit 3
GPB [4] ENC_OUT[4] Bidirectional(Input) Monitor: cipher output bit 4
GPB [5] ENC_OUT[5] Bidirectional(Input) Monitor: cipher output bit 5
GPB [6] ENC_ACTIVE_LBD_N Bidirectional(Input) Monitor: Cypher-Output activity sideband (active-LOW)
GPB [7] NC Output MCP23017 silicon restriction: GPB[7] output-only (DS20001952D §1); NC

GPA[7] and GPB[7] output-only. Both NC on U6. All 14 active monitoring signals occupy GPA[0:6] and GPB[0:6] only — no silicon violation.

U7 — MCP23017T-E/SO @ 0x21

Handles CM5 virtual-key injection, mux-select, CPLD_RESET_N output, activity monitoring, and the BOARD_ROLE_ID compatibility comparator result.

Address: 0x21 — A2=LOW, A1=LOW, A0=HIGH

Port Pin Signal Direction Notes
GPA [0] CM5_KEY_DATA[0] Bidirectional(Output) CM5 virtual-key bus bit 0 — driven to keyboard-source mux (U4/U5) input
GPA [1] CM5_KEY_DATA[1] Bidirectional(Output) CM5 virtual-key bus bit 1
GPA [2] CM5_KEY_DATA[2] Bidirectional(Output) CM5 virtual-key bus bit 2
GPA [3] CM5_KEY_DATA[3] Bidirectional(Output) CM5 virtual-key bus bit 3
GPA [4] CM5_KEY_DATA[4] Bidirectional(Output) CM5 virtual-key bus bit 4
GPA [5] CM5_KEY_DATA[5] Bidirectional(Output) CM5 virtual-key bus bit 5
GPA [6] KEY_CM5_ACTIVE Bidirectional(Output) Mux select: LOW = physical keyboard forwarded; HIGH = CM5 virtual-key forwarded
GPA [7] CPLD_RESET_N Output Board-level active-low system reset; drives CPLD DEV_CLR_N via Q1 open-drain → U3 AND gate; GPA[7] output-only — assignment is silicon-compatible
GPB [0] CM5_KEY_ACTIVE_N Bidirectional(Output) CM5 virtual-key activity sideband (active-LOW); forwarded by mux when KEY_CM5_ACTIVE=HIGH
GPB [1] KEY_SRC_ACTIVE_N Bidirectional(Input) Selected keyboard-source activity state monitoring (post-mux, active-LOW)
GPB [2] HID_VARIANT_ID[0] Bidirectional(Input) From CPLD U1: resolved BOARD_ROLE_ID compatibility result bit 0 - see §3a
GPB [3] HID_VARIANT_ID[1] Bidirectional(Input) From CPLD U1: resolved BOARD_ROLE_ID compatibility result bit 1 - see §3a
GPB [4] HID_VARIANT_ID[2] Bidirectional(Input) From CPLD U1: resolved BOARD_ROLE_ID compatibility result bit 2 - see §3a
GPB [5] HID_VARIANT_ID[3] Bidirectional(Input) From CPLD U1: resolved BOARD_ROLE_ID compatibility result bit 3 - see §3a
GPB [6] NC Bidirectional Not connected
GPB [7] NC Output MCP23017 silicon restriction: GPB[7] output-only (DS20001952D §1); NC

GPA[7] = CPLD_RESET_N (Output) — silicon-compatible. GPB[7] NC. GPB[5:2] carry HID_VARIANT_ID[3:0] (see §3a) - all bidirectional pins remain silicon-compatible.

U8 — MCP23017T-E/SO @ 0x22

CPLD configuration output driver: delivers CFG_ROUTE[3:0] and CFG_APPLY_N. GPB[5:0] is not connected - see §3 Configuration Bank 2.

Address: 0x22 — A2=LOW, A1=HIGH, A0=LOW

Port Pin Signal Direction Notes
GPA [0] CFG_ROUTE[0] Bidirectional(Output) CPLD routing config bit 0; 10 kOhm pull-down R13 on CPLD input
GPA [1] CFG_ROUTE[1] Bidirectional(Output) CPLD routing config bit 1; 10 kOhm pull-down R14 on CPLD input
GPA [2] CFG_ROUTE[2] Bidirectional(Output) CPLD routing config bit 2; 10 kOhm pull-down R15 on CPLD input
GPA [3] CFG_ROUTE[3] Bidirectional(Output) CPLD routing config bit 3; 10 kOhm pull-down R16 on CPLD input
GPA [5:4] NC Bidirectional Not connected
GPA [6] CFG_APPLY_N Bidirectional(Output) Active-low Stator-only config reload pulse; ANDed with CPLD_RESET_N through U3 to drive CPLD DEV_CLR_N; 10 kOhm pull-up R17 to 3V3_ENIG
GPA [7] NC Output MCP23017 silicon restriction: GPA[7] output-only (DS20001952D §1); NC
GPB [5:0] NC Bidirectional Not connected (see §3 Configuration Bank 2)
GPB [6] NC Bidirectional Not connected
GPB [7] NC Output MCP23017 silicon restriction: GPB[7] output-only (DS20001952D §1); NC

All 5 active signals (CFG_ROUTE[3:0] + CFG_APPLY_N) occupy GPA[0:3] and GPA[6] only — no silicon violation.

JTAG Hub

  • Chain order (all "static" CPLDs precede the "dynamic" Rotor stack): FT232H (U17) drives J6 TDI (device 1 entry, via the Hub Connector Template) → User Settings Module relays this to whichever HID board self-identifies as the Input-role board (device 1, Cypher-Input CPLD) → Cypher-Input CPLD TDO → USM relays this to whichever HID board self-identifies as the Output-role board (device 2, Cypher-Output CPLD) → Cypher-Output CPLD TDO → USM relays this back to J6 TDO → Mount1 TDI (device 3) → Mount1 TDO → Mount2 TDI (device 4) → Mount2 TDO → Mount3 TDI (device 5) → Mount3 TDO → Mount4 TDI (device 6) → Mount4 TDO → this board's own U1 CPLD TDI (device 7) → U1 TDO → J3 TTD pin → 30x Rotor CPLDs (devices 8–37) → J4 TTD_RETURN → R50 (22 Ohm) → U17 TDO. U1 sits between the 4 Plugboard Encoder Modules and the Rotor mini-stack chain. See User_Settings_Module/Design_Spec.md §4 for the Input/Output sub-chain routing within USM, and Board_Layout.md §5 for this board's own J6 pin-level wiring.

  • JTAG series termination at encoder-equivalent ports (all BtB — 33 Ohm per DEC-024):

    • TCK, TMS, CPLD_RESET_N: broadcast from the JTAG Hub via individual 33 Ohm series resistors to J3, J6 (USM Hub connector), and DF40C Mounts 1–4 (one per port) — not chained, each port gets its own dedicated wire from the hub.
    • TDI/TDO (TTD): daisy-chained port-to-port entirely via traces on this board (J6 to Mount1, Mount1 to Mount2, etc.), per the chain order above — series resistors in the R24–R29 range; exact RefDes mapping to be finalised at schematic capture. The Cypher-Input/Cypher-Output sub-chain hop (device 1 to device 2) is realised entirely within the User Settings Module and the two HID boards' own wiring, not on this board's own copper.

  • JTAG pull resistors (placed near U1):

    • R2: 10 kOhm pull-up on TTD_RETURN near J4 mating edge (idle-bias for the disconnected/bench-test state, e.g. Stack-Blanking Board plugged directly into J3/J4 with no mini-stacks attached; mirrors the R51/ACTUATE_REQUEST_OUT_N idle-bias rationale). Not related to the Controller dock — TTD_RETURN never leaves this board; the USB-JTAG bridge and full JTAG chain entry are entirely native to the Cypher Board.
    • R3: 10 kOhm TMS pull-up to 3V3_ENIG (idle TAP reset)
    • R4: 10 kOhm TDI pull-up to 3V3_ENIG (holds TDI at logic-1 / BYPASS when idle)
    • R5: 10 kOhm TCK pull-down to GND (prevents spurious clocking)
    • R6: 10 kOhm CPLD_RESET_N pull-up to 3V3_ENIG (CPLD out of reset by default)

    R3-R6 provide the broadcast net's master idle-bias at the hub itself (the signals' origin point) - this is independent of, and not redundant with, the User Settings Module's own local R1-R3 termination (User_Settings_Module/Design_Spec.md §4), which exists to give the USM branch a defined idle state if the hub side is ever disconnected during bench testing.

  • JTAG trace width: all JTAG traces routed per GRS §2.3.x targeting 50 Ohm CI.

4. Signal Turnaround (Reflector Responsibility)

The Cypher Board provides the electrical return point at the end of the rotor stack — the role of the physical Reflector (Umkehrwalze) of the historical Enigma machine.

  • Turnaround path: ENC return signals arrive via J4 (Stack-Output/REF-side QSS-025). The reflection map is applied by CPLD U1 at Step 2 of the routing matrix (§3). ENC_OUT_REF[5:0] and ENC_IN_REF[5:0] remain part of the active signal path in all supported configurations.
  • TTD_RETURN damping: R50 (22 Ohm, 0603, ERJ-3EKF2200V) — series damping on TTD_RETURN from J4 to FT232H U17 TDO. Provides impedance damping at the final rotor output.
  • Power entry: 3V3_ENIG (8 pins on J4, matching J3's power pin count for this single-rail connector) feeds the Stack-Output side of the rotor stack; no 5V_MAIN on this connector, per Stack-Output/Design_Spec.md DR-SOUT-07. See DEC-092.
  • Actuation-request chain (J4): ACTUATE_REQUEST_REF_IN_N/ACTUATE_REQUEST_REF_OUT_N occupy the same pin positions as J3's ACTUATE_REQUEST_IN_N/ACTUATE_REQUEST_OUT_N (board-agnostic template), but are logically distinct nets — the full end-to-end signal path (originating at J3, traversing the entire Rotor Mini-Stack chain and the Stack-Blanking Board, arriving here as ACTUATE_REQUEST_REF_IN_N, processed by CPLD U1's firmware, and re-emitted as ACTUATE_REQUEST_REF_OUT_N) is documented in DEC-093.
  • ESD protection on J4: U13–U16 (TPD4E05U06QDQARQ1 x4). Per DEC-045, DEC-048, and DEC-092. Placed within 3mm of J4 mating edge.
    • U13: channels — TTD_RETURN + ENC_IN[0–2] (return)
    • U14: channels — ENC_IN[3–5] (return) + ENC_OUT[0] (return)
    • U15: channels — ENC_OUT[1–4] (return)
    • U16: channels — ENC_OUT[5] (return) + ACTUATE_REQUEST_REF_IN_N + ACTUATE_REQUEST_REF_OUT_N (1 channel spare)

J4 pinout: canonical map owned by Stack-Output/Board_Layout.md §1 (DEC-094); this board's own wiring notes at Board_Layout.md §3.

5. USB-JTAG Bridge

Core Logic

  • Bridge IC: FT232H (U17, LQFP-48) in MPSSE mode. Presents as FTDI JTAG device to OpenOCD via libftdi; no custom driver required. ftdi_sio for USB enumeration; OpenOCD with libftdi for JTAG/MPSSE operation.
  • MPSSE signal mapping: AD0 = TCK; AD1 = TDI; AD2 = TDO; AD3 = TMS.
  • Buffer: SN74LVC2G125DCUR (U18, VSSOP-8) — dual-channel 3-state buffer for TCK and TMS. 1OE and 2OE tied to GND (always enabled). Buffers for 37-device JTAG chain load.
  • Crystal: 435F12012IET (Y1, 12MHz, SMD-5032). FT232H internal PLL requires 12MHz.

Power Architecture

FT232H U17 operates entirely from 3V3_ENIG — no 5V rail is required anywhere on this board's USB-JTAG bridge (Rev C silicon; see DR-CYP-11):

  • VREGIN (pin 40): 3V3_ENIG from J1 dock.
  • VCCD (pin 39): an input, tied directly to 3V3_ENIG, alongside VCCIO/VPLL/VPHY.
  • VCCIO (pins 12/24/46), VPLL (pin 8), VPHY (pin 3): all 3V3_ENIG (sets JTAG signal voltage to match CPLD I/O).
  • VCCA (pin 37), VCORE (pin 38): driven by the FT232H's internal 1.8V LDO output (derived from VREGIN); no external supply connection.
  • C28–C36 (9x 100nF 0402): per-IC bypass — one per FT232H supply pin (VCCA, VCORE, VCCD, VCCIOx3, VPLL, VPHY) + JTAG buffer U18 VCC bypass.
  • FT232H operates in USB self-powered mode (EEPROM configured accordingly). The FT232H's PWRSAV#/ACBUS7 self-powered VBUS-loss detection feature is not used — USB is entirely internal between this board and the CM5 (no external cable/connector), so there is no real VBUS-loss condition to detect.

USB Connectivity

USB D+/D- route from FT232H U17 via J2 CTL signal dock (Samtec QTS-025-01-L-D-RA-P) through the Controller Board PCB to the CM5 USB 2.0 port. USB connection is entirely internal; no USB-C connector on this board. CM5 enumerates FT232H on Linux boot via ftdi_sio; no board-side power sequencing required.

JTAG Signal Conditioning

  • R42 (33 Ohm): series damping on FT232H TDI output (within 2mm of FT232H TDI pin). Source impedance: FT232H (~20 Ohm) + R42 (33 Ohm) ~= 53 Ohm.
  • R43 (33 Ohm): series damping on U18 TCK output. Source impedance: U18 (~15 Ohm) + R43 ~= 48 Ohm.
  • R44 (33 Ohm): series damping on U18 TMS output — same function as R43.
  • R45 (33 Ohm): TDI series damping before first CPLD in chain (U1 input).
  • R46 (10 kOhm): TMS pull-up near U1 — holds JTAG TAP in defined state when idle.
  • R47 (10 kOhm): TCK pull-down near U1 — prevents spurious clocking when idle.
  • R48 (10 kOhm): FT232H RESET_N pull-up (pin 34) to 3V3_ENIG. Holds RESET_N HIGH (deasserted) per FTDI AN_108. Floating RESET_N risks chip latching in reset.

Crystal Load Capacitors

C37, C38 (33pF C0G 0402): crystal load capacitors for Y1. Crystal specifies C_L = 20pF.

  • C_series = 33/2 = 16.5pF
  • C_stray ~= 3–4pF (PCB traces + FT232H XTIN input capacitance)
  • C_L = 16.5 + 3.5 = 20pF — correct. Do not substitute 15pF (gives C_L ~= 11pF, well below spec).

FT232H Special Pins

  • REF pin (pin 5): R49 (12 kOhm ±1%, ERJ-2RKF1202X) to GND. Sets USB 2.0 HS PHY internal bias reference current. Required per FTDI FT232H datasheet §3.5 and AN_146. Without R49, HS chirp negotiation fails and device falls back to Full-Speed or fails to enumerate entirely.
  • TEST pin (pin 42): tied directly to GND by PCB copper trace. No series component. Must be GND for normal operation per FTDI datasheet Table 3.2. Floating TEST activates factory test mode and corrupts USB enumeration.

6. Interconnects

J1 / J2 — Controller Dock

  • J1 (power-only dock): Molex 2195620015. Zero signal contacts — 5x GND (power-pitch), 8x 5V_MAIN + 7x 3V3_ENIG (signal-pitch, 4.5A/contact rated). Mating CTL receptacle: Molex 2195630015.
  • J2 (signal-only dock): Samtec QTS-025-01-L-D-RA-P. Zero power rails — USB_D_PLUS/ USB_D_MINUS (to FT232H U17), I2C1_SDA/SCL (active Cypher-peripherals bus), I2C2/I2C3/ I2C4/I2C6 SDA/SCL (reserved/NC), PWM0[0-3] + GPCLK[0]/GPCLK[1] (reserved, to bare test pads), remaining pins GND. Mating CTL receptacle: Samtec QSS-025-01-L-D-A-GP-K. See DEC-098.

Pinout: see Board_Layout.md §1.

J3 — Stack-Input / STA-Side Stacking Connector (KBD_ENC / Rotor-1 group)

Connector definition owner: Stack-Input/Board_Layout.md §1 (IC-STA-CHAIN, per DEC-094). Mates with Stack-Input Board front-face male QTS-025.

  • MPN: QSS-025-01-L-D-A-GP-K (Samtec 50-contact 0.635mm vertical female SMT)
  • Stacking height: 5.00mm mated per Samtec datasheet.

Pinout: see Stack-Input/Board_Layout.md §1 for the full canonical pin map; Board_Layout.md §2 of this board for Cypher's own local wiring notes. Fully 50-pin allocated per DEC-090/DEC-093.

J4 — Stack-Output / REF-Side Stacking Connector (Reflector return group)

Connector definition owner: Stack-Output/Board_Layout.md §1 (IC-REF-CHAIN, per DEC-094). Mates with Stack-Output Board front-face male QTS-025.

  • MPN: QSS-025-01-L-D-A-GP-K (Samtec 50-contact 0.635mm vertical female SMT)

Pinout: see Stack-Output/Board_Layout.md §1 for the full canonical pin map; Board_Layout.md §3 of this board for Cypher's own local wiring notes. Fully 50-pin allocated per DEC-092/DEC-093.

J5 — Cypher Left Pair Template (Cypher-Input / Cypher-Output HID Interconnect)

Connector definition owner: this board. Mates with whichever HID board's top (right-angle male, QTS-025-01-L-D-RA-P) connector is physically closest - the other HID board attaches further down the local stack via that board's own bottom connector, not directly to this board.

  • MPN: QSS-025-01-L-D-A-GP-K (Samtec 50-contact 0.635mm vertical female SMT)
  • Carries 3V3_ENIG/5V_MAIN/GND, ENC_DATA_IN[5:0]/ENC_DATA_OUT[5:0], ENC_ACTIVE_INPUT_N/ENC_ACTIVE_OUTPUT_N, and BOARD_ROLE_ID_IN[3:0]/BOARD_ROLE_ID_OUT[3:0].
  • Top row = Cypher-Input's own signals (KBD_ENC); bottom row = this board's own generated signals bound for Cypher-Output (LBD_DEC) - see §3 CPLD Signal Routing Matrix.
  • Either HID board can occupy the position closest to this board; chaining passthrough pins on each HID board's own connectors allow both orders.

Pinout: see Board_Layout.md §4.

J6 — User Settings Module Hub Connector

Connector definition owner: User_Settings_Module/Board_Layout.md §2 (its own J1) - this board owns only its own physical connector placement and gender, per that shared template.

  • MPN: QSS-025-01-L-D-A-GP-K (Samtec 50-contact 0.635mm vertical female SMT)
  • Mates USM's own top (right-angle male, QTS-025-01-L-D-RA-P) Hub connector.
  • Carries 3V3_ENIG, the dedicated Cypher-peripherals I2C bus, and JTAG (TDI/TDO/TMS/TCK/ CPLD_RESET_N). USM relays this bus and JTAG onward to both HID boards and to Cypher-Plugboard - see §3 JTAG Hub and User_Settings_Module/Design_Spec.md §4.

Pinout: see Board_Layout.md §5 for this board's own wiring; full pin numbering owned by User_Settings_Module/Board_Layout.md §2.

J7–J18 — ENC Module Mounts (x4, back face)

Four Hirose DF40C BtB receptacle sets on the back face. Each mount accepts one ENC module serving a plugboard cipher role. Stator port group names are carried forward as labels.

Mount Refs Stator Port Group Connector A (90-pin) Connector B (24-pin) Connector C (10-pin)
1 J7, J8, J9 PLG_PASS1_DEC DF40C-90DS-0.4V(51) DF40C-24DS-0.4V(51) DF40C-10DS-0.4V(51)
2 J10, J11, J12 PLG_PASS1_ENC DF40C-90DS-0.4V(51) DF40C-24DS-0.4V(51) DF40C-10DS-0.4V(51)
3 J13, J14, J15 PLG_PASS2_DEC DF40C-90DS-0.4V(51) DF40C-24DS-0.4V(51) DF40C-10DS-0.4V(51)
4 J16, J17, J18 PLG_PASS2_ENC DF40C-90DS-0.4V(51) DF40C-24DS-0.4V(51) DF40C-10DS-0.4V(51)

Per-mount connector function:

  • Connector A (90-pin): plain-bits[63:0] interface (ENC module to Cypher Board). 2 rows x 45 positions. 64 signal pins + 26 GND pins; zig-zag GND distribution (max signal-only gap = 1 column between any two GND columns). Pin assignments (C01–C45, Row A/B) defined in Encoder_Module/Board_Layout.md §1a.
  • Connector B (24-pin): cypher-bits[5:0] (6) + JTAG (TCK, RST_N/CPLD_RESET_N, TMS, TDI, TDO = 5) + ENC_ACTIVE_N (1) + GND (12). Full zig-zag: every signal paired with GND in adjacent row position. Pin assignments defined in Encoder_Module/Board_Layout.md §1b.
  • Connector C (10-pin): 3V3_ENIG power only (5x 3V3_ENIG + 5x GND). Pin assignments defined in Encoder_Module/Board_Layout.md §1c.

Connector definition ownership: ENC module owns the interface family (DF40C-xDP plugs) - see Encoder_Module/Design_Spec.md §4 and Encoder_Module/Board_Layout.md §1a-1c. Cypher Board carries the mating DF40C-xDS receptacles.

J20+ — Spade Blade Terminal Bank (back face)

Jack plug harness attachment points on the back face, located along the bottom edge of that face (the HID/USM interconnect connectors, J5/J6, are at the top edge of the same face - see Board_Layout.md §4-§5) - this is a general placement decision only; exact per-terminal arrangement within that bottom-edge region is TBD at schematic/layout time.

  • MPN: 1285-ST (Keystone Electronics) — 6.35mm PCB spade blade terminal, THT vertical
  • DigiKey PN: 36-1285-ST-ND
  • Mouser PN: 534-1285-ST
  • JLCPCB PN: C5370868
  • Quantity: 64 per ENC module mount position x 4 mounts = 256 terminals total
  • RefDes: J20+ (exact allocation and physical arrangement TBD at schematic capture time)

Trace routing from spade blade terminals to relevant CPLD signal nets is done within the Cypher Board copper layers. The physical plugboard patch jacks are not on this board - they are mounted on the Cypher-Plugboard board (mechanical mounting only, no electrical connection to that board's own circuitry - see Cypher-Plugboard/Design_Spec.md §3 Signal Routing) and wired back to this spade bank via discrete spade-to-spade jumper cables, per DEC-088.

7. Power Telemetry

  • Sensor: INA219AIDR (U2, SOIC-8) on 3V3_ENIG rail before rotor stack distribution. I²C address 0x40 on the I2C1 bus (A0/A1 both tied to GND — INA219 default, no address-strap components required). Minimum 15mm isolation from U1 CPLD core.
  • Shunt: KRL6432T4-M-R010-F-T1 (R1, 10 mOhm ±1% 2W, 6432/2512 Kelvin 4-terminal). Rotor rail budgeted at 1.65A (30 rotors x 55mA); 2.05A worst-case including CPLDs and encoders (~32% headroom vs 3.0A LDO).
  • Ferrite beads: L1–L4 (HI1206P121R-10, 120 Ohm @100MHz, 4.0A rated). Four beads between J2 dock 3V3_ENIG entry and rotor stack distribution (~413mA per bead nominal; well within 3.5A rating).
  • RC input filter (INA219): R39 (10 Ohm RF1, series on IN+), R40 (10 Ohm RF2, series on IN-), C21 (100nF CF, differential across IN+/IN-). f_3dB ~= 80kHz differential. Suppresses electromechanical rotor noise per INA219 datasheet Figure 14.
  • Per-IC VDD bypass: C14–C20 (7x 100nF 0402) — one per Stator-local IC (U2–U8). Within 1mm of IC Vcc pin per GRS §3.2.
  • Rail entry decoupling (Bulk Entry Bank Rule per GRS §3):
    • C9–C13: 5x 10uF X7R 25V 1206 at J1 5V_MAIN entry.
    • C22–C26: 5x 10uF X7R 25V 1206 at J1 3V3_ENIG entry.
  • JTAG TTD_RETURN pull-up: R2 (10 kOhm) near J4 mating edge (idle-bias for the disconnected state). See JTAG Hub note in §3.

8. Thermal & ESD

  • Thermal: No active cooling required. Relies on chassis airflow.
  • ESD — J3 Stack-Input/STA-side (TVS required): J3 carries JTAG, ENC, and actuation-request signals; accessible during live mini-stack swap. Per DEC-045, DEC-048, and DEC-091:
    • U9: 1x TPD4E05U06QDQARQ1 — channels: TTD, TMS, TCK, CPLD_RESET_N (JTAG group)
    • U10: 1x TPD4E05U06QDQARQ1 — channels: ENC_IN[0–3]
    • U11: 1x TPD4E05U06QDQARQ1 — channels: ENC_IN[4–5] + ENC_OUT[0–1]
    • U12: 1x TPD4E05U06QDQARQ1 — channels: ENC_OUT[2–5]
    • U19: 1x TPD4E05U06QDQARQ1 — channels: ACTUATE_REQUEST_IN_N, ACTUATE_REQUEST_OUT_N (2 channels used, 2 spare) All U9–U12, U19 placed within 3mm of J3 mating edge on L1.
  • ESD — J4 Stack-Output/REF-side (TVS required): per §4 Signal Turnaround.
  • Working voltage note: TPD4E05U06QDQARQ1 max continuous working voltage = 5.5V. On 3V3_ENIG (max 3.465V at +5%), all U9–U16, U19 are within rated limits with >= 2.0V margin.
  • ESD — all other connectors (no TVS required): J1, J2 (blind-mate dock); J5, J6 (internal BtB); J7–J18 (back-face mounts, not live-swap); J20+ (passive blade terminals — ESD TBD at harness definition). Per design/Standards/Global_Routing_Spec.md §9.

9. PCB Fabrication & Stackup

  • Stackup: 6-layer / 2oz copper per design/Standards/Global_Routing_Spec.md §2.3.4. Layer assignment: L1 Signal/front face → L2 GND → L3 Inner signal (CI) → L4 Power → L5 GND → L6 Signal/back face. CI trace widths TBD with PCBWay impedance tool at board layout time.
  • Manufacturer: PCBWay for prototype. JLCPCB not suitable (6-layer + double-sided assembly).
  • Fillets: 2.0mm rounded PCB corners.
  • Mounting Holes: MH1–MH4, M3 PTH (3.2mm drill), tied to GND_CHASSIS per GRS §4. Placement pattern per GRS §4.3 (TBD — board shape not yet finalised). No BOM entry.
  • Decoupling and bulk entry capacitors: per design/Standards/Global_Routing_Spec.md §3.

10. Branding & Traceability

  • Data Plate: Per GRS §6 on bottom layer (L6). Revision block: CHIFFRIERWERK [Cypher Board] V1.0.
  • Connector Pin-1 Markers: J1–J18, J20+ silkscreen pin-1 markers required per GRS §7.1.

11. Bill of Materials

RefDes Specification MPN Manufacturer DigiKey PN Mouser PN JLCPCB PN Alt Supplier + PN Notes Footprint Available Footprint Downloaded Qty
C1-C8, C14-C21, C28-C36 100nF X7R 50V 0402 CL05B104KB5NNNC Samsung 1276-CL05B104KB5NNNCCT-ND 187-CL05B104KB5NNNC C960916 - CPLD bypass (C1-C8, C14-C21); FT232H per-IC bypass (C28-C36) ✔ ✔ 25
C9-C13, C22-C26 10µF X7R 50V 1206 CL31B106KBK6PJE Samsung 1276-CL31B106KBK6PJECT-ND 187-CL31B106KBK6PJE C43935922 – Bulk entry decoupling at J1 (5V_MAIN and 3V3_ENIG) ✔ ✔ 10
C37, C38 33pF C0G/NP0 0402 crystal-load C0402C330J5GAUTO Kemet 399-12979-1-ND 80-C0402C330J5GAUTO C2169327 - Y1 crystal load caps; C_L = 20pF ✔ ✔ 2
J1 5-pwr+15-sig press-fit hybrid plug 2195620015 Molex 900-2195620015-ND 538-219562-0015 - Global sourcing Power-only CTL dock: 5x GND (power-pitch), 8x 5V_MAIN + 7x 3V3_ENIG (signal-pitch). Mating CTL receptacle 2195630015. ✔ Pending 1
J2 50-contact 0.635mm right-angle male SMT QTS-025-01-L-D-RA-P Samtec QTS-025-01-L-D-RA-P-ND 200-QTS02501LDRAP C7267889 - Signal-only CTL dock: USB D+/D-, I2C, PWM/GPCLK reserved. Mating CTL receptacle QSS-025-01-L-D-A-GP-K. Same part as Cypher-Input/Cypher-Output J4/J5. ✔ ✔ 1
TP1-TP6 Bare copper test-pad loop - - - - - - PWM0[0-3] + GPCLK[0]/GPCLK[1] test access from CTL J2. No component; no BOM entry. - - 6
TP7-TP12 Bare copper test-pad loop - - - - - - GND test-pad loops, one paired with each of TP1-TP6. No component; no BOM entry. - - 6
J3, J4 50-contact 0.635mm vertical female SMT QSS-025-01-L-D-A-GP-K Samtec QSS-025-01-L-D-A-GP-K-ND 200-QSS02501LDAGPK C6632602 - Stack-Input/STA-side (J3); Stack-Output/REF-side (J4) ✔ ✔ 2
J5, J6 50-contact 0.635mm vertical female SMT QSS-025-01-L-D-A-GP-K Samtec QSS-025-01-L-D-A-GP-K-ND 200-QSS02501LDAGPK C6632602 - J5: Cypher Left Pair Template (whichever HID board is closest); J6: User Settings Module Hub connector; same part as J3/J4 ✔ ✔ 2
J7, J10, J13, J16 90-pin 0.4mm pitch BtB receptacle DF40C-90DS-0.4V(51) Hirose 26-DF40C-90DS-0.4V(51)CT-ND 798-DF40C90DS0.4V51 C2911197 - ENC mount plain-bits connector — Mounts 1/2/3/4 ✔ ✔ 4
J8, J11, J14, J17 24-pin 0.4mm pitch BtB receptacle DF40C-24DS-0.4V(51) Hirose H11621CT-ND 798-DF40C24DS0.4V51 C424640 - ENC mount cypher-bits + JTAG — Mounts 1/2/3/4 ✔ ✔ 4
J9, J12, J15, J18 10-pin 0.4mm pitch BtB receptacle DF40C-10DS-0.4V(51) Hirose H11617CT-ND 798-DF40C10DS0.4V51 C424636 - ENC mount power — Mounts 1/2/3/4 ✔ ✔ 4
J20+ 6.35mm PCB spade blade terminals THT vertical 1285-ST Keystone Electronics 36-1285-ST-ND 534-1285-ST C5370868 - Jack plug harness; 64 per ENC mount x 4 = 256 total; RefDes/arrangement TBD at schematic ✔ ✔ 256
L1-L4 120Ω @100MHz 4.0A 1206 ferrite bead HI1206P121R-10 Laird Performance Materials 240-2410-1-ND 875-HI1206P121R-10 C2442103 - 3V3_ENIG rotor power entry beads ✔ ✔ 4
Q1 BSS138 N-ch MOSFET SOT-23 BSS138LT1G ON Semiconductor BSS138LT1GOSCT-ND 863-BSS138LT1G C6568483 - CPLD_RESET_N open-drain buffer; prevents MCP23017 IOL overload (30-rotor stack) ✔ Pending 1
R1 10mΩ ±1% 2W 6432 (2512) Kelvin 4-terminal shunt KRL6432T4-M-R010-F-T1 Susumu KRL6432T4-M-R010-F-T1 754-KRL6432T4MR010FT C4076514 - Rotor stack current shunt ✔ ✔ 1
R2-R6, R13-R16, R36-R38, R46-R48 10kΩ 1% 0402 ERJ-2RKF1002X Panasonic P10.0KLCT-ND 667-ERJ-2RKF1002X C191123 - JTAG/config pull-ups and pull-downs (R2-R6/R13-R16/R36-R38: CPLD/config; R46-R48: FT232H idle biasing). RefDes range R18-R23 is not populated - see Configuration Bank 2 ✔ ✔ 16
R7-R12, R24-R35, R42-R45 33Ω 1% 0402 ERJ-2RKF33R0X Panasonic P33.0LCT-ND 667-ERJ-2RKF33R0X C278594 - JTAG BtB series termination 33Ω per DEC-024 (R7-R12/R24-R35: encoder-equiv ports; R42-R45: FT232H JTAG outputs) ✔ ✔ 22
R39, R40 10Ω 1% Thin-Film 0402 ERJ-2RKF10R0X Panasonic P10.0LCT-ND 667-ERJ-2RKF10R0X C413044 - INA219 RF input filter ✔ ✔ 2
R41 100Ω 1% 0402 ERJ-2RKF1000X Panasonic P100LCT-ND 667-ERJ-2RKF1000X C25190 - Q1 gate resistor (CPLD_RESET_N open-drain buffer) ✔ Pending 1
R49 12kΩ ±1% 0402 ERJ-2RKF1202X Panasonic P12.0KLCT-ND 667-ERJ-2RKF1202X C25741 - FT232H REF pin bias (pin 5 to GND); per FTDI datasheet §3.5 and AN_146 ✔ ✔ 1
R50 22Ω 1% 0603 ERJ-3EKF2200V Panasonic P220HCT-ND 667-ERJ-3EKF2200V C403073 - TTD_RETURN end-of-chain series damping (J4 to FT232H U17 TDO) ✔ ✔ 1
R51 10kΩ 1% 0402 ERJ-2RKF1002X Panasonic P10.0KLCT-ND 667-ERJ-2RKF1002X C191123 - ACTUATE_REQUEST_OUT_N (J3 pin 35) idle-bias pull-up to 3V3_ENIG; round-trip completion check input to CPLD U1. Per DEC-097. ✔ ✔ 1
U1 MAX II 570 LEs CPLD TQFP-100 EPM570T100I5N Intel (Altera) 544-2281-ND 989-EPM570T100I5N C27319 - Signal routing and reflector-mapping CPLD ✔ ✔ 1
U2 Current monitor I2C SOIC-8 INA219AIDR Texas Instruments 296-23978-1-ND 595-INA219AIDR C138706 - Rotor stack current/power telemetry ✔ ✔ 1
U3 Single AND gate SOT-23-5 SN74LVC1G08DBVR Texas Instruments 296-11601-1-ND 595-SN74LVC1G08DBVR C7666 - CPLD_RESET_N / CFG_APPLY_N AND gate ✔ ✔ 1
U4, U5 Quad 2-to-1 mux TSSOP-16 74HC157PW-Q100,118 Nexperia 1727-74HC157PW-Q100,118CT-ND 771-74HC157PWQ100118 C546614 - Keyboard source select mux ✔ ✔ 2
U6-U8 I2C GPIO expander SOIC-28 MCP23017T-E/SO Microchip Technology MCP23017T-E/SOCT-ND 579-MCP23017T-E/SO C47023 - I2C expanders (U6 @ 0x20, U7 @ 0x21, U8 @ 0x22) ✔ ✔ 3
U9-U12 4-ch bidirectional ESD array USON-10 TPD4E05U06QDQARQ1 Texas Instruments 296-40696-1-ND 595-PD4E05U06QDQARQ1 C81353 - J3 Stack-Input/STA-side ESD protection ✔ ✔ 4
U13-U16 4-ch bidirectional ESD array USON-10 TPD4E05U06QDQARQ1 Texas Instruments 296-40696-1-ND 595-PD4E05U06QDQARQ1 C81353 - J4 Stack-Output/REF-side ESD protection ✔ ✔ 4
U19 4-ch bidirectional ESD array USON-10 TPD4E05U06QDQARQ1 Texas Instruments 296-40696-1-ND 595-PD4E05U06QDQARQ1 C81353 - J3 Stack-Input/STA-side ESD protection: ACTUATE_REQUEST_IN_N/OUT_N (2 channels used, 2 spare). See DEC-091. ✔ ✔ 1
U17 USB 2.0 to MPSSE bridge LQFP-48 FT232HL-REEL FTDI Chip 768-1101-1-ND 895-FT232HL-REEL C51997 - USB-JTAG bridge in MPSSE mode ✔ ✔ 1
U18 Dual 3-state buffer VSSOP-8 SN74LVC2G125DCUR Texas Instruments 296-SN74LVC2G125DCURCT-ND 595-SN74LVC2G125DCUR C21404 - JTAG TCK/TMS output buffer (1OE/2OE tied to GND) ✔ ✔ 1
Y1 12MHz 20pF ±20ppm SMD-5032 (5.0×3.2×1.1mm) 435F12012IET CTS 110-435F12012IETTR-ND 774-435F12012IET C19766404 (Extended) - FT232H reference crystal; load caps C37/C38 = 33pF (C_L = 20pF) Yes* Yes* 1