Page Index - ml7715/VERI-Laboratory GitHub Wiki
45 page(s) in this GitHub Wiki:
- Home
- Link: https://github.com/ml7715/VERI-Laboratory/wiki
- Contents:
- PART I - Schematic to Verilog
- PART II - Counters and FSMs
- PART III - Analogue I/O and SPI serial Interface
- PART IV - Real-time Audio Signal Processing
- Experiment 10: Interface with the MCP4911 Digital to Analogue Converter
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- Experiment 11: D to A conversion using pulse width modulation
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- Experiment 12: Designing and testing a sinewave table in ROM
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- Experiment 13: A fixed frequency sinewave generator
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- Experiment 14: A variable sinewave generator
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- Experiment 15: Using the A to D converter
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- Experiment 16: An audio in and out (all pass) loop
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- Experiment 17: Echo Synthesizer with fixed delay
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- Experiment 18: Multiple echoes
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- Experiment 19: Echo Synthesizer
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- Experiment 1: Schematic capture using Quartus II 7 Segment Display
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- Experiment 2: 7 Segment decoder in Verilog HDL
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- Experiment 3: 10 bit binary switch values on three 7 segment displays
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- Experiment 4: Displaying 10 bit binary as BCD digits on the 7 segment displays
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- Experiment 5: Designing a Counter
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- Experiment 6: Implementing a 16 bit counter on DE1
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- Experiment 7: Linear Feedback Shift Register (LFSR) and PRBS
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- Experiment 8: Starting line delay circuit
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- Experiment 9: A Reaction Meter
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