Experiment 9: A Reaction Meter - ml7715/VERI-Laboratory GitHub Wiki

This experiment consists in extending the circuit of Experiment 8 to create a reaction counter. The purpose of this circuit is to count the time between all the LEDs turning OFF and the pressure of KEY[0]. The reaction time of the use will be displayed on the 7-segment displays in milliseconds.

In order to count the reaction time a a counter_16 block was created. The counter was implemented as a fsm with two states: COUNTING = 1'b1 and IDLE = 1'b0 . Two inputs start and stop drive the logic of the counter. the verilog implementation of the block is the following:

module counter_16(clock, start, stop, count);

	parameter BIT_SZ = 16;
	input clock, start, stop;
	output [BIT_SZ-1:0] count;
	
	reg [BIT_SZ-1:0] count;
	
	reg state;
	
	parameter COUNTING = 1'b1, IDLE = 1'b0;
	
	initial count = 0;
	initial state = IDLE;
	
	always @ (posedge clock)
		case(state)
			IDLE:
				if(start == 1'b1)
					begin
						count <= 0;
						state <= COUNTING;
					end
			COUNTING:
				if(stop == 1'b1)
					state <= IDLE;
				else
					count <= count + 1'b1;
		endcase
	
endmodule

The rest of the blocks were not changed and were reused in the new design. The different blocks were then linked together with a top verilog design:

module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);
	
	input CLOCK_50;
	input [3:0] KEY;
	output [9:0] LEDR;
	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
	
	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
	wire [5:0] N;
	wire [6:0] bcd_to_hex;
	wire [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
	wire [15:0] count_out;
	
	tick_50000 TICK0(CLOCK_50, tick_ms);
	
	formula_fsm FSM(tick_ms, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
	
	LFSR LFSR0(tick_ms, en_lfsr, N);
	
	delay DEL0(tick_ms, N, start_delay, time_out);
	
	counter_16 COUNT0(tick_ms, time_out, ~KEY[0], count_out);
	
	bin2bcd_16 BCD(count_out, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
	
	hex_to_7seg SEG0(HEX0, BCD_0);
	hex_to_7seg SEG1(HEX1, BCD_1);
	hex_to_7seg SEG2(HEX2, BCD_2);
	hex_to_7seg SEG3(HEX3, BCD_3);
	hex_to_7seg SEG4(HEX4, BCD_4);
	hex_to_7seg SEG5(HEX5, 4'b0);
	
endmodule

The output on the 7-segment displays is driven by the counter_16 block, and display the value of the counter.

The input and outputs were assigned to the FPGA using the pin_assignment txt file. The design was then compiled and sent to the FPGA. The result obtained was the one expected.

When KEY[3] is pressed the LEDs start lighting up one after the other.

When the LEDs turn off the counter starts counting the amount of microseconds elapsed until KEY[0] is pressed.