Experiment 5: Designing a Counter - ml7715/VERI-Laboratory GitHub Wiki

In order to generate an 8-bit binary counter a new project was created and the verilog code provided in the lab booklet was entered as the main design:

`timescale 1ns / 100ps //Unit time is 1ns, resolution 100ps

module counter_8(
    clock,   //clock input
    enable,  //high enable counting
    count    //count value
);

//--Declare ports--

   parameter BIT_SZ = 8;
   input clock, enable;
   output [BIT_SZ-1:0] count;

//count needs to be declared as reg
   reg [BIT_SZ-1:0] count;

//---always initialise storage elements such as D-FF---
   initial count = 0;

//---Main body of the module---
   always @ (posedge clock)
      if(enable == 1'b1)
         count <= count + 1'b1;

endmodule //end of module

The module was then analyzed and synthesised in order to simulate the counter using the RTL Simulation tool. Running the tool a new session a Modelsim is started. counter_8 was then selected as the verilog module to simulate and the following commands were entered in order to drive the simulation:

add wave clock enable
add wave -hexadecimal count
force clock 0 0, 1 10ns -repeat 20ns
force enable 1
run 100ns

The commands entered create a clock enable wave and an hexadecimal count wave; the clock is driven with a 50Mhz symmetrical signal; the counter is enabled and the simulation is then run for 100ns.

The output obtained was the following:

In order to simulate the counter more easily a do-file was created with the following commands:

add wave clock enable
add wave -hexadecimal count
force clock 0 0, 1 10ns -repeat 20ns
force enable 1
run 100ns
force enable 0
run 100ns
force enable 1
run 1000ns

The do-file was then saved and executed:

vsim> restart
vsim> do ./tb_counter.do

Finally the step command was used to examine how the output produced changed as we step through the verilog code simulated: