Experiment 11: D to A conversion using pulse width modulation - ml7715/VERI-Laboratory GitHub Wiki

In this experiment additional circuitry was added to the design of Experiment 10 to generate an analogue signal using pulse-width modulation and a lowpass filter.

The circuit is described by the following schematics:

The pwm module was implementing using the verilog code give in Lecture 9 slide 15:

module pwm(clk, data_in, load, pwm_out);

	input clk;
	input [9:0] data_in;
	input load;
	output pwm_out;
	
	reg[9:0] d;
	reg [9:0] count;
	reg pwm_out;
	
	always @ (posedge clk)
		if(load == 1'b1) d <= data_in;
		
	initial count = 10'b0;
	
	always @ (posedge clk) begin
		count <= count + 1'b1;
		if(count > d)
			pwm_out <= 1'b0;
		else
			pwm_out <= 1'b1;
		end
		
endmodule

The pwm module produces a signal which stays to 1 for a period of time which depends on the the data_in input transferred. The other modules were obtained during the previous experiments.

A top module was then generated to link all the blocks together:

module ex11(CLOCK_50, SW, DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT);

	input CLOCK_50;
	input [9:0] SW;
	output DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT;
	
	wire load;
	
	tick_5000 t(CLOCK_50, load);
	spi2dac s(CLOCK_50, SW, load, DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);
	pwm p(CLOCK_50, SW, load, PWM_OUT);
	
endmodule

The oscilloscope was used to measure the voltage ranges at TP9. The output ranges from 0V to 3.3V as expected.