Experiment 14: A variable sinewave generator - ml7715/VERI-Laboratory GitHub Wiki

This experiment consists in creating a variable sinewave generator. In order to do so on every sample period the address of the ROM generated in Experiment 12 is advanced by a value specified by the switches.

We know that in Experiment 13 the address of the ROM is increased by the counter every 10^-4 seconds, therefore the sampling frequency is 10kHz; we take 1024 samples, so the frequency of the signal produced is 10000/1024. If we increase the address by an arbitrary value each time, then the frequency of the wave will be multiplied by SW[9:0]*10000/1024.

In order to implement the circuit the following block diagram was provided:

The constant multiplied was generated using the IP catalog tool. The multiplier multiplies the binary value of SW by 14'd10000. The top 14-bits are then shown on the 7-seg display and corresponds to the frequency of the wave generated. By taking the top 14-bits of the result we are effectively shifting the result right by 10 bits; the value of SW is therefore multiplied by 10000/1024, which is what we wanted to accomplish.

The different blocks of the circuit were linked together using the following top verilog module:

module ex14(CLOCK_50, SW, DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT, HEX0, HEX1, HEX2, HEX3, HEX4);

	input CLOCK_50;
	input [9:0] SW;
	output DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT;
	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;
	
	wire load;
	wire [9:0] data;
	wire [9:0] address;
	wire [23:0] freq_tmp;
	wire [19:0] freq_fin;
	
	tick_5000 tick(CLOCK_50, load);
	
	add_offset fin_address(SW, load, address);
	
	ROM rom(address, CLOCK_50, data);
	
	spi2dac dac(CLOCK_50, data, load, DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);
	pwm p(CLOCK_50, data, load, PWM_OUT);
	
	const_mult mult(SW, freq_tmp);
	
	bin2bcd_16 bcd(freq_tmp[23:10], freq_fin[3:0], freq_fin[7:4], freq_fin[11:8], freq_fin[15:12], freq_fin[19:16]);
	
	hex_to_7seg h0(HEX0, freq_fin[3:0]);	
	hex_to_7seg h1(HEX1, freq_fin[7:4]);
	hex_to_7seg h2(HEX2, freq_fin[11:8]);
	hex_to_7seg h3(HEX3, freq_fin[15:12]);
	hex_to_7seg h4(HEX4, freq_fin[19:16]);
	
endmodule

The design was then compiled and sent to the FPGA.

A 439Hz sinewave was produced by setting the switched to 10'b101101. The oscilloscope was then used to verify that the sinewave produced was the one we expected:

The frequency obtained is the one we expected. The segmented sine wave on the top is generated by the DAC(TP8) while the smooth sinewave is generated by the pwm(TP9).