Experiment 4: Displaying 10 bit binary as BCD digits on the 7 segment displays - ml7715/VERI-Laboratory GitHub Wiki

In order to design a 10-bit binary to BCD converted the basic blog add3_ge5 was designed. The block adds 3 to the input when it is bigger then 5, and mirrors the input to the output otherwise. This prevents each of the outputs to the 7-segment displays to be greater than 9 as they represent binary coded decimal. The basic functionality of the add3_ge5 block is the following: as each of the bits of the initial binary number is shifted one position to the left a decimal step is performed when necessary, as we can see illustrated in the image below.

The implementation of the module in verilog is the following:

module add3_ge5(w,a);
	output [3:0] a;
	input [3:0] w;
	
	reg [3:0] a;
	
	always @ (w)
		case(w)
			4'b0000: a <= 4'b0000;
			4'b0001: a <= 4'b0001;
			4'b0010: a <= 4'b0010;
			4'b0011: a <= 4'b0011;
			4'b0100: a <= 4'b0100;
			4'b0101: a <= 4'b1000;
			4'b0110: a <= 4'b1001;
			4'b0111: a <= 4'b1010;
			4'b1000: a <= 4'b1011;
			4'b1001: a <= 4'b1100;
			4'b1010: a <= 4'b1101;
			4'b1011: a <= 4'b1110;
			4'b1100: a <= 4'b1111;
			
			default: a <= 4'b0000;
		endcase
endmodule

The basic block designed was then used in the top design linking each sub-component as illustrated in the design below, reducing the scheme to 10-bits and removing unnecessary components.

The implementation in the verilog is the following:

module bin2bcd_10 (B, BCD_0, BCD_1, BCD_2, BCD_3);

	input [9:0]	B;		// binary input number
	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3;   // BCD digit LSD to MSD
	
	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
	wire [3:0]	a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12;

	// Instantiate a tree of add3-if-greater than or equal to 5 cells
	//  ... input is w_n, and output is a_n
	add3_ge5 A1 (w1,a1);
	add3_ge5 A2 (w2,a2);
	add3_ge5 A3 (w3,a3);
	add3_ge5 A4 (w4,a4);
	add3_ge5 A5 (w5,a5);
	add3_ge5 A6 (w6,a6);
	add3_ge5 A7 (w7,a7);
	add3_ge5 A8 (w8,a8);
	add3_ge5 A9 (w9,a9);
	add3_ge5 A10 (w10,a10);
	add3_ge5 A11 (w11,a11);
	add3_ge5 A12 (w12,a12);
		
	// wire the tree of add3 modules together
	assign  w1 = {1'b0, B[9:7]};		// wn is the input port to module An
	assign  w2 = {a1[2:0], B[6]};
	assign  w3 = {a2[2:0], B[5]};
	assign  w4 = {1'b0, a1[3], a2[3], a3[3]};
	assign  w5 = {a3[2:0], B[4]};
	assign  w6 = {a4[2:0], a5[3]};
	assign  w7 = {a5[2:0], B[3]};
	assign  w8 = {a6[2:0], a7[3]};
	assign  w9 = {a7[2:0], B[2]};
	assign  w10 = {1'b0, a4[3], a6[3], a8[3]};
	assign  w11 = {a8[2:0], a9[3]};
	assign  w12 = {a9[2:0], B[1]};
	
	// connect up to four BCD digit outputs	
	assign BCD_0 = {a12[2:0],B[0]};
	assign BCD_1 = {a11[2:0],a12[3]};
	assign BCD_2 = {a10[2:0],a11[3]};
	assign BCD_3 = {3'b000,a10[3]};	
endmodule

The design was then compiled. The compilation report obtained was the following:

On the other hand compiling the 16-bit binary to BCD design we obtain:

As we can see the 16-bit module uses the same resources as the 10-bit one as Quartus optimized the the design after recognizing that six inputs were conntected to ground and only 12 of the outputs were connected to output pins in the FPGA.

For inputs of 16-bits or lower we can therefore use the 16-bit version of the design.