Experiment 2: 7 Segment decoder in Verilog HDL - ml7715/VERI-Laboratory GitHub Wiki

A new project ex2 was created and ex2_top was set as the top-level module of this project. After doing so a new module ex_to_7seg.v was created in Quartus:

module hex_to_7seg (out, in);

	output [6:0] out;
	input [3:0] in;
	
	reg [6:0] out;
	
	always @ (*)
		case(in)
			4'h0: out = 7'b1000000;
			4'h1: out = 7'b1111001;
			4'h2: out = 7'b0100100;
			4'h3: out = 7'b0110000;
			4'h4: out = 7'b0011001;
			4'h5: out = 7'b0010010;
			4'h6: out = 7'b0000010;
			4'h7: out = 7'b1111000;
			4'h8: out = 7'b0000000;
			4'h9: out = 7'b0011000;
			4'ha: out = 7'b0001000;
			4'hb: out = 7'b0000011;
			4'hc: out = 7'b1000110;
			4'hd: out = 7'b0100001;
			4'he: out = 7'b0000110;
			4'hf: out = 7'b0001110;
		endcase
endmodule

The module created implements a truth table which maps a 4 bit binary input to correspondent hexadecimal value to display on the seven segment display.

The Analyze Currrent File utility was then used to detect any errors in the verilog file. The top design was then defined in verilog and the original ex2_top bdf file was removed from the file hierarchy.

module ex2(SW, HEX0);

	input [3:0] SW;
	output [6:0] HEX0;
	
	hex_to_7seg SEG0(HEX0, SW);

endmodule

Instead of using the pin assignment editor as done in the previous experiment, the pin_assignment.txt file was downloaded from the lab webpage and imported in the ex2_top.qsf file. In this way the pins required by the experiments are assigned automatically by the qsf file.

The complete design was then compiled and transferred to the FPGA. The solution worked as expected.

The verilog modules created were moved to the "my_lib" folder to be ready available for the next experiments.