Experiment 16: An audio in and out (all pass) loop - ml7715/VERI-Laboratory GitHub Wiki

In order to complete this experiment a prototype project was downloaded from the experiment webpage.

The prototype provided implements the following schematics:

The different block of the design are connected by a top design in verilog. In order to provide a more precise and safer module declaration the signal names are explicitly defined:

	spi2adc SPI_ADC (				
		.sysclk (CLOCK_50), 
		.channel (1'b1), 
		.start (tick_10k),
		.data_from_adc (data_in),
		.data_valid (data_valid),
		.sdata_to_adc (ADC_SDI),
		.adc_cs (ADC_CS),
		.adc_sck (ADC_SCK),
		.sdata_from_adc (ADC_SDO));

The main part of the design is the processing unit (processor), which modifies the input audio signal and produces the wanted output.

In this case the processing unit is an allpass circuit, which allows the input signal to reach the output unchanged. Let us examine the verilog definition of the module:

module processor (sysclk, data_in, data_out);

	input		sysclk;		// system clock
	input [9:0]	data_in;	// 10-bit input data
	output [9:0] 	data_out;	// 10-bit output data

	wire			sysclk;
	wire [9:0]		data_in;
	reg [9:0] 		data_out;
	wire [9:0]		x,y;

	parameter 		ADC_OFFSET = 10'h181;
	parameter 		DAC_OFFSET = 10'h200;

	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
	
	assign y = x;
	
	//  Now clock y output with system clock
	always @(posedge sysclk)
		data_out <=  y + DAC_OFFSET;
		
endmodule

As we can see the design executes the following steps:

• The 10-bit input is continuously read by the module; a combinatorial circuit subtracts the 10'h181 offset from the value obtained from the ADC converter to obtain the input value in 2's complement (x);
• the elaborated signal y is connected to x as no changes are made to the signal;
• a 10'h200 offset is added to y in order to prepare the signal to be transmitted to the DAC unit;
• during each positive edge of the 50Mhz clock the output data_out is updated.

The design was compiled and sent to the FPGA. The digital design samples the input audio at 10kHz using the ADC and passes it to the output through the DAC unit.

The design was then extended: the processor module was modified in order to amplify the input signal by a factor of four.

The verilog design of the new processing unit is the following:

module processor (sysclk, data_in, data_out);

	input				sysclk;		// system clock
	input [9:0]		data_in;		// 10-bit input data
	output [9:0] 	data_out;	// 10-bit output data

	wire				sysclk;
	wire [9:0]		data_in;
	reg [9:0] 		data_out;
	wire [9:0]		x,y;

	parameter 		ADC_OFFSET = 10'h181;
	parameter 		DAC_OFFSET = 10'h200;

	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
	
	// This part should include your own processing hardware 
	// ... that takes x to produce y
	// ... In this case, it is ALL PASS.
	assign y = x << 2;
	
	//  Now clock y output with system clock
	always @(posedge sysclk)
		data_out <=  y + DAC_OFFSET;
		
endmodule

In order to multiply the intensity of the input signal by 4, the 2's complement representation of the input was shifted left by 2.

The design was compiled and sent to the FPGA. The output signal obtained was the one expected: the audio output obtained was either amplified or distorted.