Experiment 1: Schematic capture using Quartus II 7 Segment Display - ml7715/VERI-Laboratory GitHub Wiki

In order to get familiar with the tool used in the experiment a sample compiled project "ex1sol.sof" was downloaded from the lab webpage. The solution was then transferred to the FPGA as can be seen in the image below.

Changing the state of the four switches on the FPGA the hexadecimal number displayed on the 7-segment display is changed consequently.

The project "ex1" was then created and the target device set to Cyclone V 5CSEMA5F31C6. The circuit schematic was imported from the file included in the lab website and the logic driving out[4] was added to the circuit schematic:

After doing so a symbol was created in order to encapsulate the circuit completed previously. The symbol created was then added to the top level design and linked to input and output pins, as shown below.

The design was then compiled using the Start Analysis and Elaboration utility. After doing so the pin planner was used in order to connect the FPGA hardware to the circuit used.

The design was then compiled fully and transferred to the FPGA. The circuit works as expected on the device.

The TimeQuest Timing Analyzer tool was then used to analyze the delay of the circuit in two different conditions.

• Setting the Operation Conditions to Slow 1100mV 0°C Model the following Datasheet was obtained:

• On the other hand set the Operating Conditions to Slow 1100mV 85°C Model the following Datasheet was produced:

In the two datasheets produced RR indicates input rise time of the digital path analyzed, while RF, FR and FF represent respectively the input fall time, the output rise time and the output fall time of the digital path.

As we can see from the datasheet the 0°C Model is faster then the 85°C Model. This is because as the temperature of a circuit decreases the transition in the digital gates happens faster.

The design uses only 4 out of the 32,070 ALMs and 11 of the 457 I/O pins.