Experiment 13: A fixed frequency sinewave generator - ml7715/VERI-Laboratory GitHub Wiki

In this experiment the design of Experiment 12 was modified substituting the input provided by the slide switched with a 10-bit binary counter. The output of the ROM was then connected to the spi2dac and pwm modules. Doing so a perfect sine wave is produced at both analogue outputs.

To produce the design the following schematics were implemented:

The top design produced in verilog is the following:

module ex13(CLOCK_50, DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT);

	input CLOCK_50;
	output DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT;
	
	wire load;
	wire [9:0] data, count;
	
	tick_5000 t(CLOCK_50, load);
	
	counter_10 c(CLOCK_50, load, count);
	
	ROM r(count, CLOCK_50, data);
	
	spi2dac s(CLOCK_50, data, load, DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);
	pwm p(CLOCK_50, data, load, PWM_OUT);
	
endmodule

The oscilloscope was then used to verify that the two analogue outputs produced the sinewave as expected.

Output of DAC:

Output of pwm:

The sine waves produced have a frequency of approximately 10Hz.

The oscilloscope automatically corrected the output of the DAC to a sine wave, however the original output is not a perfect sine wave but is a segmented sine wave as we will see in the following experiments.