Experiment 6: Implementing a 16 bit counter on DE1 - ml7715/VERI-Laboratory GitHub Wiki

In order to implement the following circuit schematics the FPGA the modules created in the previous experiments were reused or slightly modified:

The counter_8 verilog file of experiment 5 was modified to generate a 16 bit counter:

`timescale 1ns / 100ps

module counter_16(clock,enable,reset,count);

	parameter BIT_SZ = 16;
	input clock, enable, reset;
	output [BIT_SZ-1:0] count;
	
	reg [BIT_SZ-1:0] count;
	
	initial count = 0;
	
	always @ (posedge clock)
		begin
			if(enable == 1'b1)
				count <= count + 1'b1;
			if(reset == 1'b1)
				count <= 16'b0;
		end
			
endmodule

In order to accomplish this the BIT_SZ parameter was increased to 16, this change was sufficient in order to increase the size of the counter.

The different modules used were then linked together using the following top verilog design:

module ex6(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4);
	
	input CLOCK_50;
	input [1:0] KEY;
	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;
	
	wire [15:0] count;
	wire tick;
	wire [3:0] b0, b1, b2, b3, b4;
	
	counter_16 C(CLOCK_50, ~KEY[0], ~KEY[1], count);
	
	bin2bcd_16 B(count, b0, b1, b2, b3, b4);
	
	hex_to_7seg SEG0(HEX0, b0);
	hex_to_7seg SEG1(HEX1, b1);
	hex_to_7seg SEG2(HEX2, b2);
	hex_to_7seg SEG3(HEX3, b3);
	hex_to_7seg SEG4(HEX4, b4);
	
endmodule

The design was then analysed and elaborated using the Quartus built in tools and the pin_assignment text file was imported into ex.qsf to assign the pins of the fpga as necessary.

The clock frequency was then set adding the following line to ex6.sdc:

create_clock -name "CLOCK_50" -period 20.000ns [get_ports{CLOCK_50}]

The complete design was then fully compiled and the Compilation Report was analyzed. The predicted maximum frequencies for this circuit under the highest and lowest temperatures are respectively:

Furthermore we can notice that the TimeQuest entry is red: this is because the longest path of the circuit takes more time to complete than the clock period allows.

The design was then sent to the FPGA and tested.

As part of the Test-yourself Task a cascade counter was created using the following circuit schematics:

In order to implement the circuit a tick_50000 module was used to reduce the clock. This will allow us to see the counter changing on the FPGA. The tick_50000 module was implemented in verilog:

module tick_50000(CLOCK_IN, CLK_OUT);

	parameter NBIT = 16;
	
	input CLOCK_IN;
	output CLK_OUT;
	
	reg [NBIT-1:0] count;
	
	reg CLK_OUT;
	
	initial 
		begin
			count = 16'd24999;
			CLK_OUT = 1'b0;
		end
	
	always @ (posedge CLOCK_IN)
		begin
			if(count == 16'b0)
				begin
					CLK_OUT <= ~CLK_OUT;
					count <= 16'd24999;
				end
			else
				begin
					count <= count - 1'b1;
				end
		end

endmodule

tick_50000 was implemented as a decreasing counter: whenever the count value reaches 0 the clock value is inverted and the count value is reset to 24999.

The top design specified was the following:

module ex6(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4);
	
	input CLOCK_50;
	input [1:0] KEY;
	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;
	
	wire [15:0] count;
	wire tick;
	wire [3:0] b0, b1, b2, b3, b4;
	
	tick_50000 tck(CLOCK_50, tick);
	
	counter_16 C(tick, ~KEY[0], ~KEY[1], count);
	
	bin2bcd_16 B(count, b0, b1, b2, b3, b4);
	
	hex_to_7seg SEG0(HEX0, b0);
	hex_to_7seg SEG1(HEX1, b1);
	hex_to_7seg SEG2(HEX2, b2);
	hex_to_7seg SEG3(HEX3, b3);
	hex_to_7seg SEG4(HEX4, b4);
	
endmodule

Instead of following the schematics the output of tick_50000 was fed directly to the clock input of counter_16 as suggested by the GTA staff in order to simplify the design and use less resources on the FPGA.

The final design was then tested on the FPGA and proved to be working.