Experiment 12: Designing and testing a sinewave table in ROM - ml7715/VERI-Laboratory GitHub Wiki

The purpose of this experiment is to create a 1Kx10 ROM containing the values of a sine wave which will drive out DAC chip.

The relationship between the contenct of the ROM and its address A[9:0] is the following:

D[9:0] = int(511*sin(A[9:0]2pi/1024)+512) An offset of 512 is added to the equation as the input of the DAC ranges from 0 to 1023

Before creating the ROM a mif file defining the content of the ROM was generated using the Matlab scipt provided on the experiment webpage.

The IP Catalog was then used to generate the ROM.v block in verilog.

To verify the functionality of the ROM a top design was created:

top design in verilog:

module ex12(CLOCK_50, SW, HEX0, HEX1, HEX2);

	input CLOCK_50;
	input [9:0] SW;
	output [6:0] HEX0, HEX1, HEX2;
	
	wire[9:0] data;

	ROM r(SW, CLOCK_50, data);

	hex_to_7seg h0(HEX0, data[3:0]);
	hex_to_7seg h1(HEX1, data[7:4]);
	hex_to_7seg h2(HEX2, {2'b0, data[9:8]});

endmodule

The value contained at the address selected using the switches is displayed on the 7-seg displays.

When selecting the address 0x3FF using the switched, the value 0x1FC is shown on the 7-seg displays as we expect.