Experiment 10: Interface with the MCP4911 Digital to Analogue Converter - ml7715/VERI-Laboratory GitHub Wiki

Experiment 10 utilizes a MCP4911 DAC to produce an analogue output. Some sections of the datasheet of the DAC were read in order to understand the behaviour of the chip and how to drive it using the FPGA.

The following scheme provides an overview of how each of the pins of the DAC is used:

• The chip select input enables the serial clock and data functions when low;
• The latch DAC input is used to transfer the input latch register to the DAC register.

The DAC is controlled using write commands, which consist of 16 bits used to configure the DAC's control and data latches. A write command consists of the following phases:

• The command is initialized by driving the CS pin low;
• the following 4 bits transferred are configuration bits;
• 12 bits representing the date are then serially transmitted to the DAC;
• bringing the LDAC pin to a low state, Vout is updated.

The write command is summarised in the following figure:

• bit 15 is active low and allows the command to be executed;
• BUF is the Input Buffer Control bit, the command will be buffered when this control bit is set to 1;
• GA is the output Gain Selection bit: when set to 0 it doubles the output gain, while it has no effect when set to 1;
• SHDN if the Output Shutdown Control bit, when set to 0 the output is not available;
• the bits marked with an X are to be ignored.

This figure represents how to configure the internal function of the DAC:

The timing information of the DAC used are the following:

In order to interact with the DAC the spi2dac was downloaded from the experiment webpage. The module takes a 10 bit number, a load command and the system clk as input and produces the required signals to drive the DAC chip.

Based on the information obtained when a word 10'h23b is sent to the DAC the following output is produced:

A project was created in Quartus to test the spi2dac module. The verilog files were downloaded from the experiment webpage, and the design was compiled. The RTL Simulation tool was then launched and the following commands executed:

add wave -position end  sysclk
add wave -position end -hexadecimal data_in
add wave -position end load
add wave -position end  dac_sdi
add wave -position end  dac_cs
add wave -position end  dac_sck
add wave -position end  dac_ld
force sysclk 1 0, 0 10ns -r 20ns
force data_in 10'h23b
force load 0
run 200ns
force load 1
run 400ns
force load 0
run 20us

The output obtained confirmed our predictions and proved the functionality of the spi2dac module.

A top level design module was then created to verify that the DAC works properly. The input obtained from the 10 SW on the FPGA was fed to the spi2dac module to produce the wanted analogue output. The following scheme was implemented in verilog:

verilog top module:

module ex10(CLOCK_50, SW, DAC_CS, DAC_SDI, DAC_LD, DAC_SCK);

	input CLOCK_50;
	input [9:0] SW;
	output DAC_CS, DAC_SDI, DAC_LD, DAC_SCK;
	
	wire load;
	
	tick_5000 t(CLOCK_50, load);
	spi2dac s(CLOCK_50, SW, load, DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);

endmodule

The design was then sent to the FPGA.

When the SW were set to 0 and 10'h377 the following values values were measured on the DVM at TP8 proving that the range of the DAC output extends from 0V to 3.3V:

In order to verify that the behaviour of the DAC is the one expected the oscilloscope was used to measure the following signals:

• DAC_SCK(TP3)

• DAC_SDI(TP1)

• DAC_CS(TP2)

The waveforms obtained correspond to those predicted by Modelsim.