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#Verilog Laboratory logbook - Marco Lavalle

Link: https://github.com/ml7715/VERI-Laboratory/wiki

Contents:

PART I - Schematic to Verilog

• Experiment 1: Schematic capture using Quartus II - 7-Segment Display
• Experiment 2: 7-Segment decoder in Verilog HDL
• Experiment 3: Test yourself - 10-bit binary switch values on three 7-segment displays
• Experiment 4: Displaying 10-bit binary as BCD digits on the 7-segment displays

PART II - Counters and FSMs

• Experiment 5: Designing a Counter
• Experiment 6: Implementing a 16-bit counter on DE1
• Experiment 7: Linear Feedback Shift Register (LFSR) and PRBS
• Experiment 8: Starting line delay circuit
• Experiment 9: A Reaction Meter

PART III - Analogue I/O and SPI serial Interface

• Experiment 10: Interface with the MCP4911 Digital-to-Analogue Converter
• Experiment 11: D-to-A conversion using pulse-width modulation
• Experiment 12: Designing and testing a sinewave table in ROM
• Experiment 13: A fixed frequency sinewave generator
• Experiment 14: A variable sinewave generator
• Experiment 15: Using the A-to-D converter

PART IV - Real-time Audio Signal Processing

• Experiment 16: An audio in-and-out (all pass) loop
• Experiment 17: Echo Synthesizer with fixed delay
• Experiment 18: Multiple echoes
• Experiment 19: Echo Synthesizer