ADC16x250 8_differential_rev_2 - david-macmahon/wiki_convert_test GitHub Wiki

NOT FOR NEW DESIGNS.

2013may Please note this board was frozen just prior to the release-to-fabrication stage. There are no plans to continue developments of this board. Confidence is high this design would work fine; attention has shifted to the ADC16x250-8_RJ45_rev_1 board for system integration reasons.

There are NO plans to release this board. It will not be fabricated. It will not be assembled.

Also known as

The official name of this board is ADC16x250-8 differential rev 2.

Alternative names are :

  • ADC8x250-8 differential rev 2
  • ADC8x500-8 differential rev 2
  • ADC4x1000-8 differential rev 2

similar ADC boards

For new designs :

NOT for new designs but listed here because these pages may include useful test results

Please see ADC16x250-8_differential_rev_1 for information on the version of the board that has been assembled and is in use at 1 early adapter observatory.

Please see ADC16x250-8_RJ45_rev_1 for information on the board that has taken the place of the ADC16x250-8 differential rev 2 board.

The primary differences between the ADC16x250 differential rev 1 and rev 2 boards are:

  • less rework to fix "features" in the schematics and place and route files
  • changes to the use of the ZDok+ pins to avoid the need for the extra 2x10 ribbon cable to deliver the LVCMOS programming signals from the host board's FPGA to the ADC ICs.
    • The rev 1 board delivered 7 line and frame clocks to the ZDok+ connector for possible use by the FPGA. It turns out these 7 differential pairs are not required to cleanly capture all the ADC IC data. Thus those 14 ZDok+ pins can be used for alternative functions.
  • a new Xilinx FPGA constraints file consistent with the new ZDok+ pin usage.

ADC16x250-8 differential rev 2 Operating Modes

  • Roach2 rev1 and Roach2 rev2
  • When using this 16 input ADC card with a Roach2 rev1 or Roach2 rev2 populated with the standard XC6VSX475T-1FFG1759C (note the -1 speed grade in the part number) the 3 operating modes will be
    • 16 inputs by 250 MSPS by 8 bits
      • actual clock rates are : 67.5 to 120 MSPS and 135 to 240 MSPS.
    • 8 inputs by 500 MSPS by 8 bits
      • actual clock rates are : 135 to 240 MSPS and 270 to 480 MSPS.
    • 4 inputs by 1000 MSPS by 8 bits.
      • actual clock rates are : 270 to 480 MSPS and 540 to 960 MSPS.
    • As of 2013feb05 most of the above operating modes have NOT been tested.
    • These slightly strange limits are set in large part by the specifications of the Xilin FPGA's mixed mode clock manager (MMCM) and the way the current version of the Yellow Block receives and uses the Hittite ADC IC's line clock (LCLK) to capture the high speed serial bit streams from the Hittite ADC IC outputs.
  • Higher speed Xilinx FPGAs such as the medium speed -2 and the fastest -3 speed grade part will work over wider frequency ranges with the same Yellow Block. The exact numbers won't be known until hardware is available in the lab to exercise.
  • Different sample rates may be supported if new versions of the Yellow Block were to be written and debugged. As of 2013apr16 there are no plans to work on such Yellow Block changes.
  • Roach1
  • The Virtex 5 FPGA, as used on the Roach1, has an LVDS interface to the ZDok+ connector pins that might not be able to run at speeds required to accept the ADC ICs' outputs at full rate. In practice we may need to limit the maximum speed to be 800 Mbps or so. We will push the maximum speed as high as possible but at some point we might need to cut our losses and move on.
  • When using this 16 input ADC card with a Roach1 the 3 operating modes MAY be restricted to something like :
    • 16 inputs by 200 MSPS by 8 bits
      • actual clock rates are : TBD
    • 8 inputs by 400 MSPS by 8 bits
      • actual clock rates are : TBD
    • 4 inputs by 800 MSPS by 8 bits
      • actual clock rates are : TBD
    • Actual maximum clock rates will only be found during the Yellow Block development and lab testing.
    • See the Roach2 section above - there may be some strange sample clock rate rules for the Roach1 too.

ADC16x250-8 differential rev 2 Gateware (aka yellow block) and Software

  • The ADC16 yellow block is currently available via:
  • Required software for run time initialization and monitoring of ADC16 designs is available via:
    • git clone git://github.com/david-macmahon/casper_adc16.git
  • The order of modes brought online has followed this general plan :
    • First focus on the 16 inputs by 250 MSPS mode for the Roach2. First Roach2 rev1, because that's the hardware in the lab then Roach2 rev2 because that is what was first deployed.
    • 8 input and 4 input wider bandwidth modes for the Roach2.
      • The test gateware, including snap data block RAM capture functions, only has a notion of 16 parallel data streams. The default ruby data readout and plot scripts assume these streams are for 16 inputs. The code will need to be revised to instead consider the data as 8 double rate or 4 quad rate streams.
    • all modes for the Roach1
    • The yellow block does, in general, almost nothing automatically. It's up to external code to suitably instruct the block to do what is required.
    • Upon power up the ADC ICs are in an undefined state. Yellow Block functions as well as user level Ruby scripts are available for the user to call to put the ADC ICs into the required mode. See above for the links to get these utilities.
    • The yellow block supports virtually all sorts of operating modes. The user selects these by writing and running python (or Ruby or ...) scripts which use katcp and tcpborphserver3 (or 2) to set the ADC16 IC registers as required.
  • To help with the basic setups known good sample Ruby scripts showing the commands to perform for *16, *8, *4 input modes will be released (at some point).
  • There will be some number of bells and whistles that might optimize performance, say by changing some analog programmable gain on some input branch, that will be left to the user to perform or not.

ADC16x250-8 differential rev 2 Inputs

  • Clock:
    • +6 dBm, 1.26 Vpeak_to_peak, sine wave into 50 ohm SMA socket connector.
    • Values down to 0 dBm are apt to be fine and is the minimum suggested input power level.
    • Values down at -3 dBm will incur an additional 6 dB in the phase noise of the on-board clock driver as well as reduced clocks at the ADC IC inputs.
    • Actual limits on the input clock level have not yet been measured in the lab. As discussed above and set by the limits of the Roach2 rev2's FPGA MMCM specifications the predicted limits are :

      • in 16 input mode: 67.5 to 120 MSPS and 135 to 240 MSPS.

      • in 8 input mode: 135 to 240 MSPS and 270 to 480 MSPS.

      • in 4 input mode: 270 to 480 MSPS and 540 to 960 MSPS

      • The ADC ICs have a programmable divider on the clock input. This divider can be 1,2,4 or 8. Thus, one could always supply a 960 MHz clock at the SMA input to the ADC16 board and then by changing this divider register select at run time the effective sample clock (240, 480 or 960 MHz) and the number of inputs/ADC IC (4 or 2 or 1) and thus one could switch between the 3 main modes without changing any cables.

      • At power up the ADC ICs are generally in the by-4 input mode. But this is not guaranteed. Depending on the system level clock distribution network and normal operating modes the max clock rate may be exceeded. No damage is expected. The current drawn from the 2.5 V rail can be significantly larger than in the operational state. Thus, the recommendation is to use the SPI interface to properly configure the ADCs into a mode compatible with the provided clock frequency.

    • 1:2 input clock balun. Different baluns may be used based on the degree of optimization for operation at a particular operating frequency. Or not.
    • 1:1 alternative input clock balun. These parts have not been tested yet, as of 2012sep10, but they general idea(hope?) is that the poor impedance match, due to the 1:1 rather than 1:2 ratio, won't cause significant problems. A serious investigation of drop in replacement parts that have 1:2 ratio and good specifications for 500-1000MHz hasn't been performed.
  • The one clock signal delivered to the board is received and then delivered to the 4 ADC IC chips via one low noise fanout buffer the Hittite Microwave HMC987LP5E
    • Analog Signals:
      • AC coupled to (approximately) 650 MHz (typical) 2 Vpeak_to_peak (+10 dBm sine wave; -2.6 dBm gaussian noise w/ crest factor 6) full scale 100 ohm differential pair
        • -0.5 to +0.5 V (+4 dBm sine wave; -8.5 gaussian noise w/ crest factor 6) centered around the user's Vcommon on each of 2 differential signals.
        • This board has AC coupling caps on each input to center the 2 differential signals around the ADC IC's Vcommon of AVDD/2 = c 1.8V/2 = 0.9V
        • The net inputs to the ADC IC pins are: +0.4 to +1.4 V for each of the 2 differential signals.
        • The input circuitry, including AC coupling caps, will be optimized for low frequency inputs (approx 400 KHz to 250 MHz). Different valued discrete components will need to be installed for optimal frequency response in different frequency ranges.
      • the board will be populated with 1 16-way connector, Samtec VRDPC-50-01-M-RA, as shown below.
      • A new version of the board will need to be made if shielded CAT5E RJ45 connectors are to be used.
      • The (SMA_to_Vport_adapter) has been made with SMA socket inputs, baluns and VPORT connector to facilitate lab testing. See that wiki page for more details.
      • Please see the test measurements below for more information on mapping from input dBms to ADC peak and rms counts and so on.
    • Power:
      • Power is delivered via the ZDok+ connector. See below for more information.
        • As of 2012sep04 only 4 different boards have been measured on the lab bench as standalone entities. There were no analog inputs and the ZDok+ outputs were also unconnected.
        • The current drawn across these boards was within 3 % of each other.
      • 5.0 VDC @ about 0.25 Amps from the ZDoK+ connector to power a linear regulator and in turn the 3.3 VDC clock distribution IC.
        • The current drawn from 5 V is pretty constant at 0.24 to 0.25 Amps for test frequencies from 30 to 1000 MHz.
      • 2.5 VDC @ about 1.4 Amps from the ZDoK+ connector to power a linear regulator and in turn the 1.8 VDC ADC ICs.
        • as discussed above, the current drawn will increase if the clock frequency is significantly faster than the limit for the x1, x2 or x4 mode of the ADC ICs. For example, if the ADC IC chips are in x4 mode but the clock frequence is 1000 MHz, or 4x the max speed of 250 MHz, the current will be about 2.0 Amps.
        • The current drawn from 2.5 V varies with the operating frequency. A sample of amps versus frequencies in MHz is : 0.15 @ 30, 0.19 @ 60, 0.38 @ 90, 0.49 @ 120, 0.61 @ 150, 0.80 @ 200, 0.98 Amps at 250 MHz.
      • 1.8 VDC @ about 0.58 Amps from the ZDok+ connector to power the digital side of the ADC ICs.
        • The current draw from 1.8 V varies with the operating frequency. A sample of amps versus frequencies in MHz is : 0.1 @ 30, 0.11 @ 60, 0.18 @ 90, 0.23 @ 120, 0.27 @ 150, 0.33 @ 200, 0.38 Amps at 250 MHz.
      • 1.5 VDC @ about 0.01 Amps (estimated) from the 10x2 cable and connector driven by the RoachN digital I/O connector. 1.5V is the Roach2 logic level.
  • Control/Config
  • ADC16x250-8 differential rev 2
    • Many ZDok+ pins became available after testing with the ADC16x250-8 differential rev 1 board and Roach2 rev1 and Roach2 rev 2 showed that the line clock (LCLK) from 1 and only 1 Hittite ADC IC, and sophisticated use of the Xilinx FPGA's run time programmable delay taps, was required to cleanly capture all the digital data bits.
    • The pin out of the ZDok+ was changed dramatically for the rev 2 board to locate the programming signals where they are first used rather than intersperse them as would happen if they were swapped in place of the no longer used Hittite ADC IC line and frame clock signals.
    • The control and configuration programming signals are A1..A4, C1..C4, D1..D4 and F1..F2. This list includes 8 spare signals.
    • Unlike the rev 1 version of the board, there is no need for an extra 10x2 programming cable.
    • See page 3 of the rev 2 pin mapping summary file.
  • LEDs
    • LEDs? the ADC16 doesn't need any stinking LEDs.

ADC16x250-8 differential rev 2 Additional Datasheets

ADC16x250-8 differential rev 2 Block Diagram and pin mappings

ADC16x250-8 differential rev 2 Design Files

  • ADC16x250-8 differential rev 2 Bill of Material (BOM)
  • ADC16x250-8 differential rev 2 Photos

ADC16x250-8 differential rev 2 Test results

  • The performance of the rev 2 board is intended to be about the same as the rev 1 board. The changes across the board revisions are primarily driven by board assembly yield and system integration issues. Not changing the performance. Please see the test results section of ADC16x250-8_differential_rev_1
  • test tone dBm to ADC rms counts across different frequencies
  • band limited noise dBm to ADC rms counts
  • allan variance test which measures the total power of a noise source as a function of time, and see where the measurements cease to improve with sqrt(time). 2012dec18 TBD.
  • spectral allan variance test which measures the ratio of one tone to another, and see where that ratio measurement stops improving with sqrt(time). 2012dec18 TBD.
  • LEDA tests
    • analog input is roughly 0 - 98 MHz with 196 MHz clock. More specifically the input is 28.186-88.000 MHz.
    • LEDA test #1 uses an analog input which switches back and forth between two noise sources of know power levels approximately 3 dB apart and record the measured ratio of these two power levels as a function of time. 2012dec18 TBD.
    • LEDA test #2 uses an analog input of some sort with known passband stability and record how the measured spectral bumps change over time. 2012dec18 TBD.
  • PAPER tests
    • see the LEDA tests above but with input in the range of 100 - 200 MHz and sampled with 200 MHz clock.
    • focus on 8 input mode for improved crosstalk.
  • generic tests
    • as above but in 4 input mode and wider bandwidth test signals.
    • test the basics with Roach2 rev2, Roach2 rev1 and Roach1 hosts.
    • wide bandwidth input with deep analog notch filter and measure amount of notch filled in.
    • IEEE Std 1241-2000

1U Enclosure changes

Please see the ADC16x250-8 differential section of the (ROACH 2 Enclosure) wiki page.

Contributors

  • Dan Werthimer
  • Aaron Parsons
  • Dave DeBoer
  • Calvin Cheng
  • Matt Dexter
  • design reviews generously provided by many of the CASPER community
  • David MacMahon

ADC16x250-8 differential rev 2 Inventory as of 2013apr14

  • no bare boards have been purchased.
  • no bare boards have been fabricated.
  • no boards will be assembled
  • no boards will be fabricated

Schedule

Here's a somewhat randomly selected dates of possible significance.

  • 2013feb27 two new versions of the board to be designed.
  • 2013mar20 ADC16x250-8 differential rev 2 PCB fabrication quotes are in hand but PO not submitted. PO will be released at some future TBD date.
  • 2013apr15 lots of wiki page changes to try to make the various board types and versions easier to follow
  • 2013may07 This board has been retired without ever being fabricated nor assembled. Attention is now on the ADC16x250-8_RJ45_rev_1 board.
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