ADC16x250 8_RJ45_rev_1 - david-macmahon/wiki_convert_test GitHub Wiki

2013aug05 32 of these boards, in 16 Roach2 rev2 systems, have been deployed as part of at 256 input correlator !!

Also known as

The official name of this board is ADC16x250-8 RJ45 rev 1.

Alternative names are :

  • ADC16x250-8 RJ45 rev 1
  • ADC8x500-8 RJ45 rev 1
  • ADC4x1000-8 RJ45 rev 1

similar ADC boards

For new designs :

NOT for new designs but listed here because these pages may include useful test results (or may be of historical interest)

This board is derived from the retired ADC16x250-8_differential_rev_1 and never actually built ADC16x250-8_differential_rev_2 boards. See those wiki pages for more information.

The primary differences relative to the older and retired ADC16x250 differential rev 1 version are:

  • 4 RJ45 input connectors fed by 4 CAT7 cables with 4 analog input pairs each instead of 1 Samtec 16 way input connector and cable.
  • less rework to fix "features" in the schematics and place and route files
  • changes to the use of the ZDok+ pins to avoid the need for the extra 2x10 ribbon cable to deliver the LVCMOS programming signals from the host board's FPGA to the ADC ICs.
    • The rev 1 board delivered 7 line and frame clocks to the ZDok+ connector for possible use by the FPGA. It turns out these 7 differential pairs are not required to cleanly capture all the ADC IC data. Thus those 14 ZDok+ pins can be used for alternative functions.
  • a new Xilinx FPGA constraints file consistent with the new ZDok+ pin usage.

Alternative ADC IC chips and specifications :

Hittite makes at least two other ADCs that are pin for pin compatible to the HMCAD1511 used on this board.

These alternative parts are the:

  • HMCAD1510.
    • maximum clock rates of 125, 250 and 500 MHz rather than 250, 500 and 1000 MHz.
    • F3dB of 500 MHz rather than 650 MHz
  • HMCAD1520
    • same maximum clock rates of 250, 500 and 1000 MHz in 8 bit mode.
    • Also has 12 bit mode with maximum clock rates of 160, 320 and 640 MSPS.
      • WARNING ! New gateware would need to be developed to support 12 bit data.
    • F3dB of 700 MHz rather than 650 MHz

As of 2014mar15 no boards have been built using any of the alternative ADC ICs.

ADC16x250-8 RJ45 rev 1 Operating Modes

  • Roach2 rev1 and Roach2 rev2
  • When using this 16 input ADC card with a Roach2 rev1 or Roach2 rev2 populated with the standard XC6VSX475T-1FFG1759C (note the -1 speed grade in the part number) the 3 operating modes will be
    • 16 inputs by 250 MSPS by 8 bits
      • actual clock rates are : 67.5 to 120 MSPS (still TBD as of 2014mar08) and 135 to 240 MSPS.
    • 8 inputs by 500 MSPS by 8 bits
      • actual clock rates are : 135 to 240 MSPS (still TBD as of 2014mar08) and 270 to 480 MSPS.
    • 4 inputs by 1000 MSPS by 8 bits.
      • actual clock rates are : 270 to 480 MSPS (still TBD as of 2014mar08) and 540 to 960 MSPS.
    • As of 2013feb05 most of the above operating modes have NOT been tested.
    • These slightly strange limits are set in large part by the specifications of the Xilin FPGA's mixed mode clock manager (MMCM) and the way the current version of the Yellow Block receives and uses the Hittite ADC IC's line clock (LCLK) to capture the high speed serial bit streams from the Hittite ADC IC outputs.
  • Higher speed Xilinx FPGAs such as the medium speed -2 and the fastest -3 speed grade part will work over wider frequency ranges with the same Yellow Block. The exact numbers won't be known until hardware is available in the lab to exercise.
  • Different sample rates may be supported if new versions of the Yellow Block were to be written and debugged. As of 2013apr16 there are no plans to work on such Yellow Block changes.
  • Roach1
  • The Virtex 5 FPGA, as used on the Roach1, has an LVDS interface to the ZDok+ connector pins that might not be able to run at speeds required to accept the ADC ICs' outputs at full rate. In practice we may need to limit the maximum speed to be 800 Mbps or so. We will push the maximum speed as high as possible but at some point we might need to cut our losses and move on.
  • When using this 16 input ADC card with a Roach1 the 3 operating modes MAY be restricted to something like :
    • 16 inputs by 200 MSPS by 8 bits
      • actual clock rates are : TBD
    • 8 inputs by 400 MSPS by 8 bits
      • actual clock rates are : TBD
    • 4 inputs by 800 MSPS by 8 bits
      • actual clock rates are : TBD
    • Actual maximum clock rates will only be found during the Yellow Block development and lab testing.
    • See the Roach2 section above - there may be some strange sample clock rate rules for the Roach1 too.

ADC16x250-8 RJ45 rev 1 Gateware (aka yellow block) and Software

  • The ADC16 yellow block is currently available via:
  • Required software for run time initialization and monitoring of ADC16 designs is available via:
    • git clone git://github.com/david-macmahon/casper_adc16.git
  • User guide (txt)
  • sample bof file (.bof.gz)
  • To get the model file for the sample bof file shown above :
  • The order of modes brought online has followed this general plan :
    • First focus on the 16 inputs by 250 MSPS mode for the Roach2. First Roach2 rev1, because that's the hardware in the lab then Roach2 rev2 because that is what was first deployed.
    • 8 input and 4 input wider bandwidth modes for the Roach2.
      • The test boffile listed above, including snap data block RAM capture functions, only has a notion of 16 parallel data streams. The default ruby data readout and plot scripts assume these streams are for 16 inputs. The ruby code has recently (2014marXX) been revised to instead consider the data as 8 double rate or 4 quad rate streams for new application specific model and bof files. A new test bof file that does correctly handle the demux by 2 and demux by 4 modes will be compiled at some point in the near future.
    • all modes for the Roach1
    • The yellow block does, in general, almost nothing automatically. It's up to external code to suitably instruct the block to do what is required.
    • Upon power up the ADC ICs are in an undefined state. Yellow Block functions as well as user level Ruby scripts are available for the user to call to put the ADC ICs into the required mode. See above for the links to get these utilities.
    • The yellow block supports virtually all sorts of operating modes. The user selects these by writing and running python (or Ruby or ...) scripts which use katcp and tcpborphserver3 (or 2) to set the ADC16 IC registers as required.
  • To help with the basic setups known good sample Ruby scripts showing the commands to perform for *16, *8, *4 input modes will be released (at some point).
  • There will be some number of bells and whistles that might optimize performance, say by changing some analog programmable gain on some input branch, that will be left to the user to perform or not.

Startup delay ambiguity

  • This ADC card has a "delay ambiguity" upon startup. It is due to a limitation of the Hittite HMCAD1511 chips.
  • These chips output pairs of their digital samples simultaneously over two high speed serial lanes, non-creatively named "A" and "B". The "first", "third", "fifth", etc. samples go out over lane A while the "second", "fourth", "sixth", etc. samples go out over lane B. The ordinal numbers in the previous sentence (e.g. "first") are in quotes because the "first" and subsequent samples are from the ADC chip's perspective after it "wakes up".
  • Within a single four channel ADC chip, there is never any delay ambiguity between the four channels. When multiple chips are used (such as the 4 chips on an ADC16 card) there is an inherent ambiguity as to whether samples corresponding to the same sample clock edge will appear in lane A or lane B.
  • For example, assume two chips have zero relative delay between their analog inputs and both start up at the exact same time such that they both take their "first" sample at t=0. The output samples S(t) would look like this:
    • ADC 0 Lane A: S(0), S(2), S(4), S(6), ...
    • ADC 0 Lane B: S(1), S(3), S(5), S(7), ...
    • ADC 1 Lane A: S(0), S(2), S(4), S(6), ...
    • ADC 1 Lane B: S(1), S(3), S(5), S(7), ...
  • On the other hand, assume that ADC 1 wakes up one sample period after ADC0. Then the outputs would look like this:
    • ADC 0 Lane A: S(0), S(2), S(4), S(6), ...
    • ADC 0 Lane B: S(1), S(3), S(5), S(7), ...
    • ADC 1 Lane A: S(1), S(3), S(5), S(7), ...
    • ADC 1 Lane B: S(2), S(4), S(6), S(8), ...
  • Any pair of corresponding S(t) samples are from the same ADC sample clock edge, but now it appears as if the signal into ADC 0 is delayed by one sample period relative to ADC 1, even though it really isn't.
  • The tests have not been performed to determine if the ADC "wakes up" when the ADC chip is physically powered up or software power cycled or software reset.
  • In either "wake up" scenario it would be very challenging to synchronize the startup of the 4 Hittite ADC chips on one ADC16 card to within better than one ADC sample period (e.g. better than 5 ns with 200 MHz sample clock). And it would be extremely challenging to do that across the 2 ADC16 cards on one ROACH2, and "impossible" to do that across multiple ROACH2s.
  • In short, this delay ambiguity is unavoidable and a post "wake up" calibration step is needed. Unfortunately, the Hittite ADCs do not provide any internal way to facilitate this calibration so it must be done by looking at the samples from correlated analog inputs. Whether those correlated analog inputs are the sky or a coupled-in common noise source that can be turned on for calibration is beyond the scope of the ADC16 card and gateware.

ADC16x250-8 RJ45 rev 1 Inputs

  • Clock:
    • +6 dBm, 1.26 Vpeak_to_peak, sine wave into 50 ohm SMA socket connector.
    • Values down to 0 dBm are apt to be fine and is the minimum suggested input power level.
    • Values down at -3 dBm will incur an additional 6 dB in the phase noise of the on-board clock driver as well as reduced clocks at the ADC IC inputs.
    • Actual limits on the input clock level have not yet been measured in the lab. As discussed above and set by the limits of the Roach2 rev2's FPGA MMCM specifications the predicted limits are :

      • in 16 input mode: 67.5 to 120 MSPS (still TBD as of 2014mar08) and 135 to 240 MSPS.

      • in 8 input mode: 135 to 240 MSPS (still TBD as of 2014mar08) and 270 to 480 MSPS.

      • in 4 input mode: 270 to 480 MSPS (still TBD as of 2014mar08) and 540 to 960 MSPS

      • The ADC ICs have a programmable divider on the clock input. This divider can be 1,2,4 or 8. Thus, one could always supply a 960 MHz clock at the SMA input to the ADC16 board and then by changing this divider register select at run time the effective sample clock (240, 480 or 960 MHz) and the number of inputs/ADC IC (4 or 2 or 1) and thus one could switch between the 3 main modes without changing any cables.

      • At power up the ADC ICs are generally in the by-4 input mode. But this is not guaranteed. Depending on the system level clock distribution network and normal operating modes the max clock rate may be exceeded. No damage is expected. The current drawn from the 2.5 V rail can be significantly larger than in the operational state. Thus, the recommendation is to use the SPI interface to properly configure the ADCs into a mode compatible with the provided clock frequency.

    • 1:2 input clock balun. Different baluns may be used based on the degree of optimization for operation at a particular operating frequency. Or not.
    • 1:1 alternative input clock balun. These parts have not been tested yet, but they general idea(hope?) is that the poor impedance match, due to the 1:1 rather than 1:2 ratio, won't cause significant problems. A serious investigation of drop in replacement parts that have 1:2 ratio and good specifications for 500-1000MHz hasn't been performed.
    • The one clock signal delivered to the board is received and then delivered to the 4 ADC IC chips via one low noise fanout buffer the Hittite Microwave HMC987LP5E
  • Analog Signals:
    • The full scale inputs to the Hittite ADC IC are (assuming single input into 50 ohm load)
      • AC coupled to (approximately) 650 MHz (typical)
      • 2 Vpeak_to_peak (+10 dBm) sine wave
      • -2.6 dBm gaussian noise w/ crest factor 6)
    • Due to the loss in the components just upstream of the ADC IC
      • the F3dB frequency of the board will be reduced, possibly considerably, relative to a Hittite ADC IC itself.
      • The full scale input level will be greater than that of the Hittite ADC IC itself.
      • See the testing section below for measured values.
      • The usable full scale range is also a function of the digital gain programmed into the ADC IC.
    • The actual ADC IC inputs are differential signals. Each of the full scale differential inputs are :
      • -0.5 to +0.5 V (+4 dBm) sine wave
      • -8.5 gaussian noise w/ crest factor 6
      • centered around the around the ADC IC's Vcommon of AVDD/2 = c 1.8V/2 = 0.9V
      • with net input to the ADC IC pins of +0.4 to +1.4 V
      • This board has AC coupling caps on each input to center the 2 differential signals around the ADC IC's Vcommon of AVDD/2 = 1.8V/2 = 0.9V
      • The input circuitry, including AC coupling caps, will be optimized for low frequency inputs (approx 400 KHz to 100 MHz). Different valued discrete components will need to be installed for optimal frequency response in different frequency ranges.
    • the board will be populated with 4 shielded CAT5E RJ45 connectors
    • Please see the test measurements below for more information on mapping from input dBms to ADC peak and rms counts and so on.
  • Power:
    • Power is delivered via the ZDok+ connector. See below for more information.
      • The measurements from the ADC16x250-8_differential_rev_1 boards is probably a valid first order estimate :
      • The current drawn across these boards was within 3 % of each other.
    • 5.0 VDC @ about 0.25 Amps from the ZDoK+ connector to power a linear regulator and in turn the 3.3 VDC clock distribution IC.
      • The current drawn from 5 V is pretty constant at 0.24 to 0.25 Amps for test frequencies from 30 to 1000 MHz.
    • 2.5 VDC @ about 1.4 Amps from the ZDoK+ connector to power a linear regulator and in turn the 1.8 VDC ADC ICs.
      • as discussed above, the current drawn will increase if the clock frequency is significantly faster than the limit for the x1, x2 or x4 mode of the ADC ICs. For example, if the ADC IC chips are in x4 mode but the clock frequence is 000 MHz, or 4x the max speed of 250 MHz, the current will be about 2.0 Amps.
      • The current drawn from 2.5 V varies with the operating frequency. A sample of amps versus frequencies in MHz is : 0.15 @ 30, 0.19 @ 60, 0.38 @ 90, 0.49 @ 120, 0.61 @ 150, 0.80 @ 200, 0.98 Amps at 250 MHz.
    • 1.8 VDC @ about 0.58 Amps from the ZDok+ connector to power the digital side of the ADC ICs.
      • The current draw from 1.8 V varies with the operating frequency. A sample of amps versus frequencies in MHz is : 0.1 @ 30, 0.11 @ 60, 0.18 @ 90, 0.23 @ 120, 0.27 @ 150, 0.33 @ 200, 0.38 Amps at 250 MHz.
  • Control/Config
  • ADC16x250-8 RJ45 rev 1
    • Many ZDok+ pins became available after testing with the ADC16x250-8_differential_rev_1 board and Roach2 rev1 and Roach2 rev 2 showed that the line clock (LCLK) from 1 and only 1 Hittite ADC IC, and sophisticated use of the Xilinx FPGA's run time programmable delay taps, was required to cleanly capture all the digital data bits.
    • The pin out of the ZDok+ was changed dramatically for the ADC16x250-8_coax_rev_2, ADC16x250-8_RJ45_rev_1 and ADC16x250-8_coax_rev_1 boards to locate the programming signals where they are first used rather than intersperse them as would happen if they were swapped in place of the no longer used Hittite ADC IC line and frame clock signals.
    • The control and configuration programming signals are A1..A4, C1..C4, D1..D4 and F1..F2. This list includes 8 spare signals.
    • Unlike the rev 1 version of the board, there is no need for an extra 10x2 programming cable.
    • See page 3 of the rev 2 pin mapping summary file.
  • LEDs
    • LEDs? the ADC16 doesn't need any stinking LEDs.

ADC16x250-8 RJ45 rev 1 Additional Datasheets

ADC16x250-8 RJ45 rev 1 Block Diagram and pin mappings

ADC16x250-8 RJ45 rev 1 Design Files

ADC16x250-8 RJ45 rev 1 Photos

bare fabricated PCB

assembled circuit board

Reworked circuit board

  • as of 2013jun07 no rework is required. Nothing to show.

Pictures of the RJ45 connectors showing the CAT7 grounding scheme

ADC16x250-8 RJ45 rev 1 Test results

  • The performance of the RJ45 rev 1 board is intended to be better in channel isolation and gain versus frequency when compared against the ADC16x250-8_differential_rev_1 board.
  • Until tests are run on the RJ45 boards please see the test results section of ADC16x250-8_differential_rev_1
  • TBD ADC rms counts versus test tone frequency. First tests have SLP70 low pass filtered noise at -6.6dBm into the SMA to RJ45 adapter and a 3 ft CAT7 cable produces ADC rms counts of 13.8 to 14.8.
  • TBD band limited noise dBm to ADC rms counts
  • min, max and rms for SLP70 signal for boards D001..D035 (PDF)
  • ADC16_cross_corr_tests
  • serial data lane calibration results for board D001..D035 (TXT)
  • allan variance test which measures the total power of a noise source as a function of time, and see where the measurements cease to improve with sqrt(time). 2013may07 TBD.
  • spectral allan variance test which measures the ratio of one tone to another, and see where that ratio measurement stops improving with sqrt(time). 2013may07 TBD.
  • generic tests
    • as above but in 4 input mode and wider bandwidth test signals.
    • test the basics with Roach2 rev2, Roach2 rev1 and Roach1 hosts.
    • wide bandwidth input with deep analog notch filter and measure amount of notch filled in.
    • IEEE Std 1241-2000

1U Enclosure changes

Please see the ADC16x250-8 RJ45 section of the ROACH 2 Enclosure wiki page.

  • 2013aug06 PDFs finally added.

Contributors

  • Dan Werthimer
  • Aaron Parsons
  • Dave DeBoer
  • Calvin Cheng
  • Matt Dexter
  • design reviews generously provided by many of the CASPER community
  • Jama Mohamed
  • Glenn Jones
  • David MacMahon
  • Zaki Ali

ADC16x250-8 RJ45 rev 1 Inventory as of 2013aug06

RAL built ADC16x250-8 RJ45 rev 1

  • 1. S/N : 001. At Digicom as a stuff and solder sample.

DigiCom built ADC16x250-8 RJ45 rev 1

  • 35. S/N D001..D035
    • D001..D019, D021..D024, and D026..D035 are the part of the 256 input LEDA-OVRO Correlator. Includes 1 spare.
    • D020 and D025 are in the RAL Dig Lab as spares and misc test boards.
    • Maybe Digicom made others ???

Schedule

Here's a somewhat randomly selected dates of possible significance.

  • 2013may07 Decision has been made to stop efforts on differential rev1 and differential rev 2 boards. RJ45 inputs it is.
  • 2013may07 start to lock down details of RJ45 to ADC IC input mapping. Wiki creation.
  • 2013may08 To fit 4 RJ45 connectors across the short free edge of the PCB requires moving the clock connector to the digital (ZDok+) side of the ADC ICs. This took a few extra unscheduled days.
  • 2013may14 released Gerber files are at the PCB vendor
  • 2013may17 Last round of emails to rectify differences between the data in the actual Gerber files versus the ascii text fab instructions. The differences due to old version of Gerber generation software which didn't correctly draw down at the 0.1mil level.
  • 2013may29 RAL to start to assemble in-house the first board then start lab tests
  • 2013jun06 first assembled board powered up with no "features". Crosscorrelation and other tests have started.
  • 2013jul16 start to inspect and test the first batch of Digicom's production run
  • 2013jul23 all 35 of 35 Digicom's boards are up and running. Ship 33 to LEDA-OVRO.
  • 2013jul31 32 ADC16x250 rj45s, 256 total inputs, are up and running as part of LEDA-OVRO
  • 2014mar09 long overdue wiki edit session
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