ADC16x250 8_differential_rev_1 - david-macmahon/wiki_convert_test GitHub Wiki

NOT FOR NEW DESIGNS.

Please note this board has been "retired" after a few boards were built and used at 2 observatories. There are no plans to assemble any more boards. Design efforts for a 16 way differential input 250MSa/sec board were redirected on 2013may07 to the ADC16x250-8_RJ45_rev_1.

Also known as

The official name of this obsolete board is ADC16x250-8 differential rev 1.

Alternative names are :

  • ADC8x250-8 differential rev 1
  • ADC8x500-8 differential rev 1
  • ADC4x1000-8 differential rev 1

similar ADC boards

For new designs :

NOT for new designs but listed here because these pages may include useful test results

Relative to the more modern boards, the ADC16x250-8_RJ45_rev_1 and ADC16x250-8_differential_rev_2, this rev 1 version uses an extra 2x10 ribbon cable to deliver the LVCMOS programming signals from the host board's FPGA to the ADC ICs. This was done so that as many of the Hittite ADC IC's output clocks could be sent over the ZDok+ connector to the FPGA. It turns out most of those clocks aren't actually used. This use of ZDok+ pins means a different Xilinx constraints file must be used when compiling a design for the different board revisions.

ADC16x250-8 differential rev 1 Operating Modes

  • Roach2 rev1 and Roach2 rev2
  • When using this 16 input ADC card with a Roach2 rev1 or Roach2 rev2 populated with the standard XC6VSX475T-1FFG1759C (note the -1 speed grade in the part number) the 3 operating modes will be
    • 16 inputs by 250 MSPS by 8 bits
      • actual clock rates are : 67.5 to 120 MSPS and 135 to 240 MSPS.
    • 8 inputs by 500 MSPS by 8 bits
      • actual clock rates are : 135 to 240 MSPS and 270 to 480 MSPS.
    • 4 inputs by 1000 MSPS by 8 bits.
      • actual clock rates are : 270 to 480 MSPS and 540 to 960 MSPS.
    • As of 2013feb05 most of the above operating modes have NOT been tested.
    • These slightly strange limits are set in large part by the specifications of the Xilin FPGA's mixed mode clock manager (MMCM) and the way the current version of the Yellow Block receives and uses the Hittite ADC IC's line clock (LCLK) to capture the high speed serial bit streams from the Hittite ADC IC outputs.
  • Higher speed Xilinx FPGAs such as the medium speed -2 and the fastest -3 speed grade part will work over wider frequency ranges with the same Yellow Block. The exact numbers won't be known until hardware is available in the lab to exercise.
  • Different sample rates may be supported if new versions of the Yellow Block were to be written and debugged. As of 2013apr16 there are no plans to work on such Yellow Block changes.
  • Roach1
  • The Virtex 5 FPGA, as used on the Roach1, has an LVDS interface to the ZDok+ connector pins that might not be able to run at speeds required to accept the ADC ICs' outputs at full rate. In practice we may need to limit the maximum speed to be 800 Mbps or so. We will push the maximum speed as high as possible but at some point we might need to cut our losses and move on.
  • When using this 16 input ADC card with a Roach1 the 3 operating modes MAY be restricted to something like :
    • 16 inputs by 200 MSPS by 8 bits
      • actual clock rates are : TBD
    • 8 inputs by 400 MSPS by 8 bits
      • actual clock rates are : TBD
    • 4 inputs by 800 MSPS by 8 bits
      • actual clock rates are : TBD
    • Actual maximum clock rates will only be found during the Yellow Block development and lab testing.
    • See the Roach2 section above - there may be some strange sample clock rate rules for the Roach1 too.

ADC16x250-8 differential rev 1 Gateware (aka yellow block) and Software

  • The ADC16 yellow block is currently available via:
  • Required software for run time initialization and monitoring of ADC16 designs is available via:
    • git clone git://github.com/david-macmahon/casper_adc16.git
  • The order of modes brought online has followed this general plan :
    • First focus on the 16 inputs by 250 MSPS mode for the Roach2. First Roach2 rev1, because that's the hardware in the lab then Roach2 rev2 because that is what was first deployed.
    • 8 input and 4 input wider bandwidth modes for the Roach2.
      • The test gateware, including snap data block RAM capture functions, only has a notion of 16 parallel data streams. The default ruby data readout and plot scripts assume these streams are for 16 inputs. The code will need to be revised to instead consider the data as 8 double rate or 4 quad rate streams.
    • all modes for the Roach1
    • The yellow block does, in general, almost nothing automatically. It's up to external code to suitably instruct the block to do what is required.
    • Upon power up the ADC ICs are in an undefined state. Yellow Block functions as well as user level Ruby scripts are available for the user to call to put the ADC ICs into the required mode. See above for the links to get these utilities.
    • The yellow block supports virtually all sorts of operating modes. The user selects these by writing and running python (or Ruby or ...) scripts which use katcp and tcpborphserver3 (or 2) to set the ADC16 IC registers as required.
  • To help with the basic setups known good sample Ruby scripts showing the commands to perform for *16, *8, *4 input modes will be released (at some point).
  • There will be some number of bells and whistles that might optimize performance, say by changing some analog programmable gain on some input branch, that will be left to the user to perform or not.

ADC16x250-8 differential rev 1 Inputs

  • Clock:
    • +6 dBm, 1.26 Vpeak_to_peak, sine wave into 50 ohm SMA socket connector.
    • Values down to 0 dBm are apt to be fine and is the minimum suggested input power level.
    • Values down at -3 dBm will incur an additional 6 dB in the phase noise of the on-board clock driver as well as reduced clocks at the ADC IC inputs.
    • Actual limits on the input clock level have not yet been measured in the lab. As discussed above and set by the limits of the Roach2 rev2's FPGA MMCM specifications the predicted limits are :

      • in 16 input mode: 67.5 to 120 MSPS and 135 to 240 MSPS.

      • in 8 input mode: 135 to 240 MSPS and 270 to 480 MSPS.

      • in 4 input mode: 270 to 480 MSPS and 540 to 960 MSPS

      • The ADC ICs have a programmable divider on the clock input. This divider can be 1,2,4 or 8. Thus, one could always supply a 960 MHz clock at the SMA input to the ADC16 board and then by changing this divider register select at run time the effective sample clock (240, 480 or 960 MHz) and the number of inputs/ADC IC (4 or 2 or 1) and thus one could switch between the 3 main modes without changing any cables.

      • At power up the ADC ICs are generally in the by-4 input mode. But this is not guaranteed. Depending on the system level clock distribution network and normal operating modes the max clock rate may be exceeded. No damage is expected. The current drawn from the 2.5 V rail can be significantly larger than in the operational state. Thus, the recommendation is to use the SPI interface to properly configure the ADCs into a mode compatible with the provided clock frequency.

    • 1:2 input clock balun. Different baluns may be used based on the degree of optimization for operation at a particular operating frequency. Or not.
    • 1:1 alternative input clock balun. These parts have not been tested yet, as of 2012sep10, but they general idea(hope?) is that the poor impedance match, due to the 1:1 rather than 1:2 ratio, won't cause significant problems. A serious investigation of drop in replacement parts that have 1:2 ratio and good specifications for 500-1000MHz hasn't been performed.
  • The one clock signal delivered to the board is received and then delivered to the 4 ADC IC chips via one low noise fanout buffer the Hittite Microwave HMC987LP5E
    • Analog Signals:
      • AC coupled to (approximately) 650 MHz (typical) 2 Vpeak_to_peak (+10 dBm sine wave; -2.6 dBm gaussian noise w/ crest factor 6) full scale 100 ohm differential pair
        • -0.5 to +0.5 V (+4 dBm sine wave; -8.5 gaussian noise w/ crest factor 6) centered around the user's Vcommon on each of 2 differential signals.
        • This board has AC coupling caps on each input to center the 2 differential signals around the ADC IC's Vcommon of AVDD/2 = c 1.8V/2 = 0.9V
        • The net inputs to the ADC IC pins are: +0.4 to +1.4 V for each of the 2 differential signals.
        • The input circuitry, including AC coupling caps, will be optimized for low frequency inputs (approx 400 KHz to 250 MHz). Different valued discrete components will need to be installed for optimal frequency response in different frequency ranges.
      • the board will be populated with 1 16-way connector, Samtec VRDPC-50-01-M-RA, as shown below.
      • A new version of the board will need to be made if shielded CAT5E RJ45 connectors are to be used.
      • The SMA_to_Vport_adapter has been made with SMA socket inputs, baluns and VPORT connector to facilitate lab testing. See that wiki page for more details.
      • Please see the test measurements below for more information on mapping from input dBms to ADC peak and rms counts and so on.
      • For information on the version of this board for inputs over CAT7 cables into a shielded CAT5E RJ45 connector please see ADC16x250-8_RJ45_rev_1
    • Power:
      • Power is delivered via the ZDok+ connector. See below for more information.
        • As of 2012sep04 only 4 different boards have been measured on the lab bench as standalone entities. There were no analog inputs and the ZDok+ outputs were also unconnected.
        • The current drawn across these boards was within 3 % of each other.
      • 5.0 VDC @ about 0.25 Amps from the ZDoK+ connector to power a linear regulator and in turn the 3.3 VDC clock distribution IC.
        • The current drawn from 5 V is pretty constant at 0.24 to 0.25 Amps for test frequencies from 30 to 1000 MHz.
      • 2.5 VDC @ about 1.4 Amps from the ZDoK+ connector to power a linear regulator and in turn the 1.8 VDC ADC ICs.
        • as discussed above, the current drawn will increase if the clock frequency is significantly faster than the limit for the x1, x2 or x4 mode of the ADC ICs. For example, if the ADC IC chips are in x4 mode but the clock frequence is 1000 MHz, or 4x the max speed of 250 MHz, the current will be about 2.0 Amps.
        • The current drawn from 2.5 V varies with the operating frequency. A sample of amps versus frequencies in MHz is : 0.15 @ 30, 0.19 @ 60, 0.38 @ 90, 0.49 @ 120, 0.61 @ 150, 0.80 @ 200, 0.98 Amps at 250 MHz.
      • 1.8 VDC @ about 0.58 Amps from the ZDok+ connector to power the digital side of the ADC ICs.
        • The current draw from 1.8 V varies with the operating frequency. A sample of amps versus frequencies in MHz is : 0.1 @ 30, 0.11 @ 60, 0.18 @ 90, 0.23 @ 120, 0.27 @ 150, 0.33 @ 200, 0.38 Amps at 250 MHz.
      • 1.5 VDC @ about 0.01 Amps (estimated) from the 10x2 cable and connector driven by the RoachN digital I/O connector. 1.5V is the Roach2 logic level.
  • Control/Config
  • ADC16x250-8 differential rev 1
    • 10x2 0.1" pitch header for ribbon cable to the host Roach2 rev 1, Roach 2 rev 2 or Roach 1.
      • cable pin mapping is 1-1, 2-2 and so on.
      • if twisted pairs are used 1 and 2, 3 and 4, and so on should be paired as the even pins are all GND.
      • if standard IDC connectors and flat ribbon cable is used the pattern will be signal/ground/signal/ground which works fine too.
      • Prototype cables of each type, twisted pair and flat ribbon, were made with lengths of 20 and 21 inches. These lengths are long enough such that either GPIO connector on a Roach2 can connect with a ADC16 card in either ZDok+ slot. Even so spare cable is left so the cable can be routed along the board edges.
      • To minimize crosstalk the plan is to set the FPGA GPIO pins to have slow slew rates and low drive strengths. There is no need to have fast edge rates traveling down this cable.
      • The mapping of host board (Roach1 or Roach2 rev1 or Roach2 rev2) GPIO pins to ADC16x250-8 cards at ZDok0 and ZDok1 connectors is fixed. In theory one could change the mapping by changing FPGA constraints files and possibly the yellow block. That is not advised.
        • See pages 6 and 7 of the block diagram PDF referenced below as well as page 3 of the pin mapping summary file.
        • Roach2 rev1 and Roach2 rev2 V6_GPIO8 .. V6_GPIO15 bits on P13 "FPGA GPIO" to ADC16x250 at P10 "ZDok0"
        • Roach2 rev1 and Roach2 rev2 V6_GPIO0 .. V6_GPIO7 bits on P15 "FPGA GPIO/LEDs" to ADC16x250 at P11 "ZDok1"
          • Note the "LEDs" suffix to the GPIO 00 to 07 pins above. The standard Roach2 1U enclosure has a IDC cable connected from P15 on the Roach2 rev2 to a small PCB mounted to the interior side of the 1U chassis' faceplate. This LED cable must be removed, at least at the Roach2 rev2 side, to make room for the ADC16x250-8 programming cable.
          • Other mechanical changes are required to the Roach2 1U enclosure to make it fully compatible with the ADC16x250-8 cards. See the ADC16x250 differential changes section ROACH_2_Enclosure wiki page.
        • Roach1 tbd_bits on J9 "FPGA GPIO A" to ADC16x250 at P5 "ZDok0"
        • Roach1 tbd_bits on J2 "FPGA GPIO B" to ADC16x250 at P7 "ZDok1"
  • LEDs
    • LEDs? the ADC16 doesn't need any stinking LEDs.

ADC16x250-8 differential rev 1 Additional Datasheets

ADC16x250-8 differential rev 1 Block Diagram and pin mappings

ADC16x250-8 differential rev 1 Design Files

ADC16x250-8 differential rev 1 Photos

bare fabricated PCB

assembled circuit board

Reworked circuit board

ADC16x250-8 differential rev 1 Test results

  • Using the SMA to Vport adapter board described below with single tones and SLP-70 LPF filtered wide band noise source the following mapping from dBm to ADC rms counts has been measured in the lab
  • During these tests the ADC IC's analog and digital gain parameters were all set to their default power-on values.
  • plot of min and max counts vs dBms for 20,50 and 70 MHz test tones (pdf)
  • 20,50,70 MHz tones and SLP70 gain table (txt)
  • SLP70 filtered noise min and max counts across 3 boards (pdf)
    • TBD: Why is board 004 input A2 so much stronger ? It may be due to pre 2013feb11 version of yellow block used for the test which had a subtle timing problem lurking in the data capture logic.
  • SLP70 filtered noise rms counts across 3 boards (pdf)
    • TBD: Why is board 004 input A2 so much stronger and board 003 input C2 so much weaker? It may be due to pre-2013feb11 version of yellow block used for the test which had a subtle timing problem lurking in the data capture logic.
  • network analyzer measurements (PDF)
    • The network analyzer measurements were not all that useful. They don't show nearly all the coupling that is shown with wide band noise inputs and a correlator as the detector.
    • The network analyzer measurements show, as expected, there is inter-channel coupling on the SMA to Vport adapter.
    • The network analyzer measurements show, as expected, there is inter-channel coupling, and loss, on the Samtec connector and cables.
    • Some of the channel pairs couple much more than others.
    • There is at least some suggestion that switching from the high density 16way Samtec connector and cable scheme to 16 individual cables will increase the inter-channel isolation.
  • ADC16_cross_corr_tests
  • allan variance test which measures the total power of a noise source as a function of time, and see where the measurements cease to improve with sqrt(time). 2012dec18 TBD.
    • spectral allan variance test which measures the ratio of one tone to another, and see where that ratio measurement stops improving with sqrt(time). 2012dec18 TBD.
    • LEDA tests
      • analog input is roughly 0 - 98 MHz with 196 MHz clock. More specifically the input is 28.186-88.000 MHz.
      • LEDA test #1 uses an analog input which switches back and forth between two noise sources of know power levels approximately 3 dB apart and record the measured ratio of these two power levels as a function of time. 2012dec18 TBD.
      • LEDA test #2 uses an analog input of some sort with known passband stability and record how the measured spectral bumps change over time. 2012dec18 TBD.
    • PAPER tests
      • see the LEDA tests above but with input in the range of 100
        • 200 MHz and sampled with 200 MHz clock.
      • focus on 8 input mode for improved crosstalk.
    • generic tests
      • as above but in 4 input mode and wider bandwidth test signals.
      • test the basics with Roach2 rev2, Roach2 rev1 and Roach1 hosts.
      • wide bandwidth input with deep analog notch filter and measure amount of notch filled in.
      • IEEE Std 1241-2000

1U Enclosure changes

Please see the ADC16x250-8 differential section of the ROACH 2 Enclosure wiki page.

Contributors

  • Dan Werthimer
  • Aaron Parsons
  • Dave DeBoer
  • Calvin Cheng
  • Matt Dexter
  • design reviews generously provided by many of the CASPER community
  • Jama Mohamed
  • Glenn Jones
  • David MacMahon
  • Zaki Ali

ADC16x250-8 differential rev 1 Inventory as of 2013apr14

RAL built ADC16x250-8 differential rev 1

  • S/N 001 LEDA New Mexico. Synergy Microwave TM2-1 balun on clock input. Initial science !
  • S/N 002 LEDA New Mexico. Synergy Microwave TM2-1 balun on clock input. Initial science !
  • S/N 003 LEDA New Mexico. Synergy Microwave TM2-1 balun on clock input. Initial science !
  • S/N 004 LEDA New Mexico. Synergy Microwave TM2-1 balun on clock input. Initial science !

DigiCom built ADC16x250-8 differential rev 1

  • S/N D001 NRAO. Mini-Circuits TC2-72T+ balun on clock input.
  • S/N D002 NRAO. Mini-Circuits TC2-72T+ balun on clock input.
  • S/N D003 CFA. Mini-Circuits TC2-72T+ balun on clock input. For LEDA OVRO.
  • S/N D004 CFA. Mini-Circuits TC2-72T+ balun on clock input. For LEDA OVRO.
  • S/N D005 CFA. Mini-Circuits TC2-72T+ balun on clock input. For LEDA OVRO.
  • S/N D006 CFA. Mini-Circuits TC2-72T+ balun on clock input. For LEDA OVRO.

Schedule

Here's a somewhat randomly selected dates of possible significance.

  • 2012apr10 first emailed description of board to be designed sent; schematic capture started.
  • 2012may30 schematics almost done; first pass of components placement on physical board is done.
  • 2012jun15 meeting to kick off the FPGA gateware aka yellow block effort
  • 2012jul09 bare PCB fabrication started (batch of 40 boards; 5 day turn around)
  • 2012jul12 solder stencil PO submitted for first boards to be hand built at RAL.
  • 2012jul27 first assembled board sent to FPGA gateware developer so they can start trying to capture ADC IC test patterns.
  • 2012sep13 learn that Samtec is switching vendors for their Vport connectors and cable assemblies; getting parts will be a hassle.
  • 2012oct15 All ADC16x250 and SMA to Vport adapter parts are at DigiCom for professional assembly.
  • 2012nov09 FPGA gateware transferred to a new developer.
  • 2012nov14 DigiCom has finished assembling 2 ADC16 cards including all subtle rework; RAL to test.
  • 2012dec20 first sampled sine wave captured in the yellow block's snap register. But still something is fishy with the data capture.
  • 2013jan08 first 1U enclosure populated with 2 ADC16x250-8 cards and clock cables, etc.
  • 2013jan22 Now that each lane, of each channel of each ADC IC of each ADC16x250-8 board, is delayed independently the FPGA is capturing clean low level bit test patterns. The yellow block supports one or two cards on Roach2 rev1 or rev2. Roach1 support is TBD.
  • 2013jan30 Initial lab testing w/ 1 ADC16 at ZDok+ 0 and analog signals. All 16 inputs are mapped correctly. Operation with 2 ADC16s installed at ZDok 0 and ZDok+ 1 attempted but needs a bit more work to get all bit streams captured cleanly.
  • 2013jan30 shipped Roach2 rev2 w/ 2 ADC16s and 2 SFP+ mezzanine cards for testing at CFA.
  • 2013jan31 Still await final decision to revise or not the prototype versions of the schematics and place and route files for manufacturing and RJ45 input connector option as well as continued Vport connector option.
  • 2013feb05 Yellow Block has revised MMCM clock capture and distribution. Overnight tests have captured 688 Gbits error free on a Roach2 rev2 testbed.
  • 2013feb14 Start testing in the lab w/ Zaki's 8 input pocket correlator PoCo single Roach2 rev1 or rev2 design for correlation measurements.
  • 2013feb27 some very simplistic crosstalk tests have been done; Independent inputs on different ADC ICs widely physically separated correlate at about -40 dB level. Independent inputs tightly spaced and on the same ADC IC more like at -20 dB level ??? Efforts continue.
  • 2013feb27 two new versions of the board to be designed. 1 with blue wire fixes and 1 with the same blue wire fixes and new analog input connections and other changes to try to reduce unwanted coupling.
  • 2013mar19 ADC16x250-8 coax rev 1 PCB fabrication PO for 20 boards (for PAPER) has been submitted.
  • 2013mar20 ADC16x250-8 differential rev 2 PCB fabrication quotes are in hand but PO not submitted. PO will be released at some future TBD date.
  • 2013apr10 ADC16x250-8 coax rev 1 S/N 001 has been assembled and is ready for testing.
  • 2013apr11 ADC16x250-8 coax rev 1 20 boards worth of SMB-SMB cables have been purchased. They may not arrive for 8 weeks.
  • 2013apr12 Hopefully, the last two ADC16x250-8 differential rev 1 boards, S/N D005 and D006, have been assembled including all rework and are ready for testing.
  • 2013apr15 lots of wiki page changes to try to make the various board types and versions easier to follow
  • 2013may07 add in links to the RJ45 rev 1 board which is the current focus of effort.
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