ROACH - david-macmahon/wiki_convert_test GitHub Wiki

ROACH (Reconfigurable Open Architecture Computing Hardware) is a standalone FPGA processing board.

History

ROACH is a Virtex5-based upgrade to current CASPER hardware. It merges aspects from the IBOB and BEE2 platforms into a single board. The CX4/XAUI/10GbE interfaces of both are kept, while combining the Z-DOK daughter board interface of the IBOB with the high bandwidth/capacity DRAM memory and standalone usage model of the BEE2. ROACH is a single-FPGA board, dispensing with the on-board inter-FPGA links in favor of 10GbE interfaces for all cross-FPGA communications.

Description

The centrepiece of ROACH is a Xilinx Virtex 5 FPGA (either LX110T for logic-intensive applications, or SX95T for DSP-slice-intensive applications). A separate PowerPC runs Linux and is used to control the board (program the FPGA and allow interfacing between the FPGA "software registers/BRAMs/FIFOs" and external devices using Ethernet).

Two quad data rate (QDR) SRAMs provide high-speed, medium-capacity memory (specifically for doing corner-turns), and one DDR2 DIMM provides slower-speed, high-capacity buffer memory for the FPGA. The PowerPC has an independent DDR2 DIMM in order to boot Linux/BORPH.

The two Z-DOK connectors allow ADC, DAC and other interface cards to be attached to the FPGA, in the same manner as the IBOB allowed (with backwards compatibility for the ADC boards used with the IBOB).

Four CX4 connectors provide a total of 40Gbits/sec bandwidth for connecting ROACH boards together, or connecting them to other XAUI/10GbE-capable devices (such as BEE2 boards, computers with 10GbE NICs and 10GbE switches).

For more detailed descriptions, see: ROACH Architecture

Specifications

• FPGA
  • 1x Xilinx Virtex-5 XC5VLX110T-1FF1136 or Virtex-5 XC5VSX95T-1FF1136 FPGA

• FPGA Interfaces
  • 2x Z-DOK+ 40 differential pair connectors
  • 4x CX4 10Gbps high-speed serial connectors
  • 1x QSH 40 differential pair connector
  • 16x GPIO
  • 4x SMA IO (2x clock-capable)

• FPGA Peripherals
  • 2x 2M x 18-bit QDRII+ SRAMs
  • 1x DDR2 DRAM DIMM

• CPU
  • 1x AMCC PowerPC 440EPx Embedded Processor

• CPU Interfaces
  • 1x RS232 DB9 serial port
  • 1x 10/100/1000Mbit RJ45 Ethernet
  • 1x USB2.0
  • 1x MMC/SD card socket

• Monitor and Management
  • Temperatures of Xilinx Virtex5, PowerPC and Actel Fusion.
  • Voltages of 12V, 5V, 3.3V, 2.5V, 1.8V, 1.5V, 1V and 1.2V aux rails.
  • Automated shutdown in the event of over temperature, over or under voltage with logging of last shutdown event.
  • Remote power on/off.
  • Separate 100Mbps Ethernet port for independent board control and health monitoring.

• Block Diagram
  • v1.02 Block Diagram (PDF)

• Schematics
  • v1.01 Schematics (PDF)
  • v1.02 Schematics (PDF)
  • v1.03 Schematics (PDF)

• Gerbers
  • v1.0.3 Gerbers, see readme for details

A free PADS PCB viewer is available from http://www.mentor.com/products/pcb-system-design/design-flows/pads/pads-pcb-viewer

Development

The details about development progression have been moved to its own dedicated page: ROACH Development.

How to get it

Production is managed by Mo at Digicom. Send production-related inquiries to mo at digicom dot org. Production is grouped into batches, so lead times are variable.

Usage Manuals, Guides, Memos, etc.

• Getting Started with ROACH.
• Latest firmware and software versions.
• Initial bringup, configuration, and test process.
• ROACH test machine.
• UBOOT and kernel update procedure.
• Setting up BORPH on ROACH.
• ROACH configuration memo (KAT-7 DBE internal memo 008).
• ROACH onboard monitor and management subsystem.
• KATCP for remote control over the network.
• ZDOK Pin Numbering.
• ROACH NFS guide
• ROACH Enclosure/Chassis.
• Latest Versions.
• ROACH DDR2 Modules.
• How to debrick your roach using an open source alternative to OCD commander.
• ROACH USB issue and workaround
• RFI Tests
• Sync inputs
  • The Roach1 has (at least) two possible sync inputs:
    • Via the vertical mount SMA receptacle connectors J12. The signal input to this connector is terminated into 50 ohms and then turned into the LVDS differential pair "GPIO_CLK0_P" and "GPIO_CLK0_N" via an Analog Devices ADCMP605BCPE comparator and enters the FPGA at pins G15/G16.
    • Via the vertical mount SMA receptacle connectors J13. The signal input to this connector is terminated into 50 ohms and then turned into the LVDS differential pair "GPIO_CLK1_P" and "GPIO_CLK1_N" via an Analog Devices ADCMP605BCPE comparator and enters the FPGA at pins H14/H15.
  • These pins are available in the standard CASPER tools libraries.

Contact

For any ROACH issues, submit questions to the CASPER Mailing List.