ADC16x250 8_coax_rev_1 - david-macmahon/wiki_convert_test GitHub Wiki

NOT FOR NEW DESIGNS.

2013may28 The first hand assembled board, out of a total of 20 blank boards was tested in the lab. All functions work without any rework of any kind. The remaining 19 could be built but will not be built by DigiCom. Instead efforts will be directed towards the ADC16x250-8_coax_rev_2 in the hopes that a bit more effort will result in increased isolation, lower coupling, across the analog inputs.

Also known as

The official name of this board is ADC16x250-8 coax rev 1.

Alternative names are :

  • ADC8x250-8 coax rev 1
  • ADC8x500-8 coax rev 1
  • ADC4x1000-8 coax rev 1

similar ADC boards

For new designs :

NOT for new designs but listed here because these pages may include useful test results

This board is a single-ended analog input version of the ADC16x250-8_differential_rev_1.

The primary differences relative to the ADC16x250-8_differential_rev_1 board are:

  • improved crosstalk or coupling specifications by delivering the 16 analog inputs to the board over 16 independent and well shielded 50 ohm coax cables rather than a single 16 way 100 ohm differential pair cable assembly.
    • Or in other words, trade off lower connector density for higher inter channel isolation.
  • NO required rework to fix "features" in the schematics and place and route files
  • changes to the ZDok+ pins to avoid the need for the extra 2x10 ribbon cable to deliver the LVCMOS programming signals from the host board's FPGA to the ADC ICs.
    • The rev 1 board delivered 7 line and frame clocks to the ZDok+ connector for possible use by the FPGA. It turns out these 7 differential pairs are not required to cleanly capture all the ADC IC data. Thus those 14 ZDok+ pins can be used for alternative functions.
  • a new Xilinx FPGA constraints file consistent with the new ZDok+ pin usage.

ADC16x250-8 coax rev 1 Operating Modes

  • Roach2 rev1 and Roach2 rev2
  • When using this 16 input ADC card with a Roach2 rev1 or Roach2 rev2 populated with the standard XC6VSX475T-1FFG1759C (note the -1 speed grade in the part number) the 3 operating modes will be
    • 16 inputs by 250 MSPS by 8 bits
      • actual clock rates are : 67.5 to 120 MSPS and 135 to 240 MSPS.
    • 8 inputs by 500 MSPS by 8 bits
      • actual clock rates are : 135 to 240 MSPS and 270 to 480 MSPS.
    • 4 inputs by 1000 MSPS by 8 bits.
      • actual clock rates are : 270 to 480 MSPS and 540 to 960 MSPS.
    • As of 2013feb05 most of the above operating modes have NOT been tested.
    • These slightly strange limits are set in large part by the specifications of the Xilin FPGA's mixed mode clock manager (MMCM) and the way the current version of the Yellow Block receives and uses the Hittite ADC IC's line clock (LCLK) to capture the high speed serial bit streams from the Hittite ADC IC outputs.
  • Higher speed Xilinx FPGAs such as the medium speed -2 and the fastest -3 speed grade part will work over wider frequency ranges with the same Yellow Block. The exact numbers won't be known until hardware is available in the lab to exercise.
  • Different sample rates may be supported if new versions of the Yellow Block were to be written and debugged. As of 2013apr16 there are no plans to work on such Yellow Block changes.
  • Roach1
  • The Virtex 5 FPGA, as used on the Roach1, has an LVDS interface to the ZDok+ connector pins that might not be able to run at speeds required to accept the ADC ICs' outputs at full rate. In practice we may need to limit the maximum speed to be 800 Mbps or so. We will push the maximum speed as high as possible but at some point we might need to cut our losses and move on.
  • When using this 16 input ADC card with a Roach1 the 3 operating modes MAY be restricted to something like :
    • 16 inputs by 200 MSPS by 8 bits
      • actual clock rates are : TBD
    • 8 inputs by 400 MSPS by 8 bits
      • actual clock rates are : TBD
    • 4 inputs by 800 MSPS by 8 bits
      • actual clock rates are : TBD
    • Actual maximum clock rates will only be found during the Yellow Block development and lab testing.
    • See the Roach2 section above - there may be some strange sample clock rate rules for the Roach1 too.

ADC16x250-8 coax rev 1 Gateware (aka yellow block) and Software

  • The ADC16 yellow block is currently available via:
  • Required software for run time initialization and monitoring of ADC16 designs is available via:
    • git clone git://github.com/david-macmahon/casper_adc16.git
  • The order of modes brought online has followed this general plan :
    • First focus on the 16 inputs by 250 MSPS mode for the Roach2. First Roach2 rev1, because that's the hardware in the lab then Roach2 rev2 because that is what was first deployed.
    • 8 input and 4 input wider bandwidth modes for the Roach2.
      • The test gateware, including snap data block RAM capture functions, only has a notion of 16 parallel data streams. The default ruby data readout and plot scripts assume these streams are for 16 inputs. The code will need to be revised to instead consider the data as 8 double rate or 4 quad rate streams.
    • all modes for the Roach1
    • The yellow block does, in general, almost nothing automatically. It's up to external code to suitably instruct the block to do what is required.
    • Upon power up the ADC ICs are in an undefined state. Yellow Block functions as well as user level Ruby scripts are available for the user to call to put the ADC ICs into the required mode. See above for the links to get these utilities.
    • The yellow block supports virtually all sorts of operating modes. The user selects these by writing and running python (or Ruby or ...) scripts which use katcp and tcpborphserver3 (or 2) to set the ADC16 IC registers as required.
  • To help with the basic setups known good sample Ruby scripts showing the commands to perform for *16, *8, *4 input modes will be released (at some point).
  • There will be some number of bells and whistles that might optimize performance, say by changing some analog programmable gain on some input branch, that will be left to the user to perform or not.

ADC16x250-8 coax rev 1 Inputs

  • Clock:
    • +6 dBm, 1.26 Vpeak_to_peak, sine wave into 50 ohm SMB jack (receptacle) connector.
    • Values down to 0 dBm are apt to be fine and is the minimum suggested input power level.
    • Values down at -3 dBm will incur an additional 6 dB in the phase noise of the on-board clock driver as well as reduced clocks at the ADC IC inputs.
    • Actual limits on the input clock level have not yet been measured in the lab. As discussed above and set by the limits of the Roach2 rev2's FPGA MMCM specifications the predicted limits are :

      • in 16 input mode: 67.5 to 120 MSPS and 135 to 240 MSPS.

      • in 8 input mode: 135 to 240 MSPS and 270 to 480 MSPS.

      • in 4 input mode: 270 to 480 MSPS and 540 to 960 MSPS

      • The ADC ICs have a programmable divider on the clock input. This divider can be 1,2,4 or 8. Thus, one could always supply a 960 MHz clock at the SMA input to the ADC16 board and then by changing this divider register select at run time the effective sample clock (240, 480 or 960 MHz) and the number of inputs/ADC IC (4 or 2 or 1) and thus one could switch between the 3 main modes without changing any cables.

      • At power up the ADC ICs are generally in the by-4 input mode. But this is not guaranteed. Depending on the system level clock distribution network and normal operating modes the max clock rate may be exceeded. No damage is expected. The current drawn from the 2.5 V rail can be significantly larger than in the operational state. Thus, the recommendation is to use the SPI interface to properly configure the ADCs into a mode compatible with the provided clock frequency.

    • 1:2 input clock balun. Different baluns may be used based on the degree of optimization for operation at a particular operating frequency. Or not.
    • 1:2 alternative input clock balun Mini-Circuits TC2-72T+ 10-700 MHz 1:2 input clock balun (PDF)
      • Note the typical output phases are within 3 degrees of 180 degrees apart from 1 to about 650 MHz.
      • As shown in the inventory section below these parts have not yet been tried on any board.
    • 1:1 alternative input clock balun. These parts have not been tested yet, as of 2012sep10, but they general idea(hope?) is that the poor impedance match, due to the 1:1 rather than 1:2 ratio, won't cause significant problems. A serious investigation of drop in replacement parts that have 1:2 ratio and good specifications for 500-1000MHz hasn't been performed.
  • The one clock signal delivered to the board is received and then delivered to the 4 ADC IC chips via one low noise fanout buffer the Hittite Microwave HMC987LP5E
  • Analog Signals:
    • AC coupled to (approximately) 650 MHz (typical) 2 Vpeak_to_peak (+10 dBm sine wave; -2.6 dBm gaussian noise w/ crest factor 6) full scale over 50 ohm coax.
    • This board has an AC coupled balun on each input to generate the 2 differential signals, -0.5 to +0.5 V (+4 dBm sine wave; -8.5 gaussian noise w/ crest factor 6), centered around the around the ADC IC's Vcommon of AVDD/2 = c 1.8V/2 = 0.9V
    • The net inputs to the ADC IC pins are: +0.4 to +1.4 V for each of the 2 differential signals.
    • The input circuitry, including balun and shunt caps, will be optimized for low frequency inputs (approx 400 KHz to 250 MHz). Different valued discrete components will need to be installed for optimal frequency response in different frequency ranges.
    • the board will be populated with 16 50ohm coaxial cables terminated with bulkhead mount jack(receptacle) SMB connectors that pass thru custom holes in the 1U chassis and are mounted to a custom 1U faceplate.
  • Power:
    • Power is delivered via the ZDok+ connector from the Host FPGA board.
    • As of 2013apr16 no power measurements have been made.
    • The power measurements are apt to be the same as on the ADC16x250-8_differential_rev_1.
  • Control/Config
  • ADC16x250-8 differential rev 2
    • Many ZDok+ pins became available after testing with the ADC16x250-8_differential_rev_1 board and Roach2 rev1 and Roach2 rev 2 showed that the line clock (LCLK) from 1 and only 1 Hittite ADC IC, and sophisticated use of the Xilinx FPGA's run time programmable delay taps, was required to cleanly capture all the digital data bits.
    • The pin out of the ZDok+ was changed dramatically for this board to locate the programming signals where they are first used rather than intersperse them as would happen if they were swapped in place of the no longer used Hittite ADC IC line and frame clock signals.
    • The control and configuration programming signals are A1..A4, C1..C4, D1..D4 and F1..F2. This list includes 8 spare signals.
    • Unlike the ADC16x250-8_differential_rev_1, there is no need for an extra 10x2 programming cable.
    • See page 3 of the rev 2 pin mapping summary file shown below.
  • LEDs
    • LEDs? the ADC16 doesn't need any stinking LEDs.

ADC16x250-8 coax rev 1 Additional Datasheets

ADC16x250-8 coax rev 1 Block Diagram and pin mappings

  • block diagram (PDF)
    • this block diagram also has SMB cable to the faceplate and ZDok+ connector routing information.
  • input coax cable diagrams (PDF)
    • This document shows how the analog coax cables map to the faceplate connectors.
    • Also shown are rough locations of the input baluns.
  • As described below, to ease routing challenges all data and clock pairs on the ADC16 board have P, N signals reversed. The

gateware (yellow block) knows about and compensates for this inversion).

ADC16x250-8 coax rev 1 Design Files

ADC16x250-8 coax rev 1 Test results

  • The performance of the coax rev 1 board is intended to be better in channel isolation and gain versus frequency when compared against the ADC16x250-8_differential_rev_1 board.
  • Until tests are run on the coax input boards please see the test results section of ADC16x250-8_differential_rev_1
  • ADC rms counts versus test tone frequency (PDF)
  • band limited noise dBm to ADC rms counts
  • ADC16_cross_corr_tests
  • allan variance test which measures the total power of a noise source as a function of time, and see where the measurements cease to improve with sqrt(time). 2013may02 TBD.
  • spectral allan variance test which measures the ratio of one tone to another, and see where that ratio measurement stops improving with sqrt(time). 2013may02 TBD.
  • PAPER tests
    • analog input is roughly 100 - 200 MHz with 200 MHz clock.
    • PAPER test #1 uses an analog input which switches back and forth between two noise sources of known power levels approximately 3 dB apart and record the measured ratio of these two power levels as a function of time. 2013apr16 TBD.
    • PAPER test #2 uses an analog input of some sort with known passband stability and record how the measured spectral bumps change over time. 2013may02 TBD.
  • generic tests
    • as above but in 4 input mode and wider bandwidth test signals.
    • test the basics with Roach2 rev2, Roach2 rev1 and Roach1 hosts.
    • wide bandwidth input with deep analog notch filter and measure amount of notch filled in.
    • IEEE Std 1241-2000

1U Enclosure changes

Please see the ADC16x250-8 differential section of the ROACH 2 Enclosure wiki page.

Contributors

  • Dan Werthimer
  • Aaron Parsons
  • Dave DeBoer
  • Calvin Cheng
  • Matt Dexter
  • design reviews generously provided by many of the CASPER community
  • Jama Mohamed
  • Glenn Jones
  • David MacMahon
  • Zaki Ali

ADC16x250-8 coax rev 1 Inventory as of 2013apr18

  • 20 bare boards have been purchased.
  • 20 bare boards have been fabricated.
  • 1 board has been assembled by RAL (only 1 SMB coax cable is at input A4)
  • 1 boards have been tested in the lab and comes up, calibrates and first test tones cleanly captured.

Schedule

Here's a somewhat randomly selected dates of possible significance.

  • 2013feb27 two new versions of the board to be designed.
  • 2013mar19 ADC16x250-8 coax rev 1 PCB fabrication PO for 20 boards (for PAPER) has been submitted.
  • 2013apr10 ADC16x250-8 coax rev 1 S/N 001 has been assembled and is ready for testing.
  • 2013apr11 ADC16x250-8 coax rev 1 20 boards worth of SMB-SMB cables have been purchased. They may not arrive for 8 weeks.
  • 2013apr11-18 lots of wiki page changes to try to make the various board types and versions easier to follow
  • 2013apr18 new Yellow Block with new ZDok+ pin out is available as well as test bof file.
  • 2013apr18 ADC16x250-8 coax rev 1 board S/N 001 powers up, calibrates and cleanly captures a 70 MHz test tone at input A4 which is the only input with a SMB input cable at the moment. Woo Hoo! Time to add on the rest of the SMB coax cable inputs.
  • 2013apr24 ADC16x250-8 coax rev 1 board S/N 001 has 16 working analog inputs, all mounted to a custom face plate, and passing valid ADC samples to the FPGA when in the ZDok+ 0 slot of a Roach2 rev 2. Now onto the more complicated tests...
  • 2013may02 first set of crosstalk measurements done but results need to be released.
  • 2013may06 A big batch of crosscorrelation results have been added to the wiki. See https://casper.berkeley.edu/wiki/ADC16_cross_corr_tests
  • 2013may07 crosscorrelation results have been reviewed and found to be a bit disappointing; a coax rev 2 board will be made. The primary change will be to space apart the baluns as much as possible, even those on opposite sides of the PCB. Test results show the balun to balun coupling is stronger than that of the differential traces between the balun and the ADC IC.
  • 2013may12 after more lab tests we may be measuring the limit of the ADC IC. It seems that there is significant coupling upstream of the analog input crossbar and somewhere downstream of the Rseries portion of the analog input subcircuit. Perhaps the ADC IC package and die at the internal track and hold receiver circuit ?
  • 2013may24 after a detour to release the ADC16x250-8_RJ45_rev_1 board the coax rev 2 board is at the board fab house.
  • 2013jun10 is the target date for RAL to start to assemble the first coax rev 2 board
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