ADC16x250 8_coax_rev_2 - david-macmahon/wiki_convert_test GitHub Wiki

Also known as

The official name of this board is ADC16x250-8 coax rev 2.

Alternative names are :

  • ADC8x250-8 coax rev 2
  • ADC8x500-8 coax rev 2
  • ADC4x1000-8 coax rev 2

similar ADC boards

For new designs :

NOT for new designs but listed here because these pages may include useful test results (or may be of historical interest)

The primary differences relative to the previous ADC16 boards, see list above, are:

  • improved crosstalk or coupling specifications by delivering the 16 analog inputs to the board over 16 independent and well shielded 50 ohm coax cables rather than 4 4 way CAT7 twisted pair cables or a single 16 way 100 ohm differential pair cables.
    • Or in other words, trade off lower connector density for higher inter channel isolation.
  • NO required rework to fix "features" in the schematics and place and route files
  • changes to the ZDok+ pins to avoid the need for the extra 2x10 ribbon cable to deliver the LVCMOS programming signals from the host board's FPGA to the ADC ICs.
    • The rev 1 board delivered 7 line and frame clocks to the ZDok+ connector for possible use by the FPGA. It turns out these 7 differential pairs are not required to cleanly capture all the ADC IC data. Thus those 14 ZDok+ pins can be used for alternative functions.
  • a new Xilinx FPGA constraints file consistent with the new ZDok+ pin usage.

Alternative ADC IC chips and specifications :

Hittite makes at least two other ADCs that are pin for pin compatible to the HMCAD1511 used on this board.

These alternative parts are the:

  • HMCAD1510.
    • maximum clock rates of 125, 250 and 500 MHz rather than 250, 500 and 1000 MHz.
    • F3dB of 500 MHz rather than 650 MHz
  • HMCAD1520
    • same maximum clock rates of 250, 500 and 1000 MHz in 8 bit mode.
    • Also has 12 bit mode with maximum clock rates of 160, 320 and 640 MSPS.
      • WARNING ! New gateware would need to be developed to support 12 bit data.
    • F3dB of 700 MHz rather than 650 MHz

As of 2014mar15 no boards have been built using any of the alternative ADC ICs.

ADC16x250-8 coax rev 2 Operating Modes

  • Roach2 rev1 and Roach2 rev2
  • When using this 16 input ADC card with a Roach2 rev1 or Roach2 rev2 populated with the standard XC6VSX475T-1FFG1759C (note the -1 speed grade in the part number) the 3 operating modes will be
    • 16 inputs by 250 MSPS by 8 bits
      • actual clock rates are : 67.5 to 120 MSPS (still TBD as of 2014mar08) and 135 to 240 MSPS.
    • 8 inputs by 500 MSPS by 8 bits
      • actual clock rates are : 135 to 240 MSPS (still TBD as of 2014mar08) and 270 to 480 MSPS.
    • 4 inputs by 1000 MSPS by 8 bits.
      • actual clock rates are : 270 to 480 MSPS (still TBD as of 2014mar08) and 540 to 960 MSPS.
    • As of 2013feb05 most of the above operating modes have NOT been tested.
    • These slightly strange limits are set in large part by the specifications of the Xilin FPGA's mixed mode clock manager (MMCM) and the way the current version of the Yellow Block receives and uses the Hittite ADC IC's line clock (LCLK) to capture the high speed serial bit streams from the Hittite ADC IC outputs.
  • Higher speed Xilinx FPGAs such as the medium speed -2 and the fastest -3 speed grade part will work over wider frequency ranges with the same Yellow Block. The exact numbers won't be known until hardware is available in the lab to exercise.
  • Different sample rates may be supported if new versions of the Yellow Block were to be written and debugged. As of 2013apr16 there are no plans to work on such Yellow Block changes.
  • Roach1
  • The Virtex 5 FPGA, as used on the Roach1, has an LVDS interface to the ZDok+ connector pins that might not be able to run at speeds required to accept the ADC ICs' outputs at full rate. In practice we may need to limit the maximum speed to be 800 Mbps or so. We will push the maximum speed as high as possible but at some point we might need to cut our losses and move on.
  • When using this 16 input ADC card with a Roach1 the 3 operating modes MAY be restricted to something like :
    • 16 inputs by 200 MSPS by 8 bits
      • actual clock rates are : TBD
    • 8 inputs by 400 MSPS by 8 bits
      • actual clock rates are : TBD
    • 4 inputs by 800 MSPS by 8 bits
      • actual clock rates are : TBD
    • Actual maximum clock rates will only be found during the Yellow Block development and lab testing.
    • See the Roach2 section above - there may be some strange sample clock rate rules for the Roach1 too.

ADC16x250-8 coax rev 2 Gateware (aka yellow block) and Software

  • The ADC16 yellow block is currently available via:
  • Required software for run time initialization and monitoring of ADC16 designs is available via:
  • User guide (txt)
  • sample bof file (.bof.gz)
  • To get the model file for the sample bof file shown above :
  • The order of modes brought online has followed this general plan :
    • First focus on the 16 inputs by 250 MSPS mode for the Roach2. First Roach2 rev1, because that's the hardware in the lab then Roach2 rev2 because that is what was first deployed.
    • 8 input and 4 input wider bandwidth modes for the Roach2.
      • The test boffile listed above, including snap data block RAM capture functions, only has a notion of 16 parallel data streams. The default ruby data readout and plot scripts assume these streams are for 16 inputs. The ruby code has recently (2014marXX) been revised to instead consider the data as 8 double rate or 4 quad rate streams for new application specific model and bof files. A new test bof file that does correctly handle the demux by 2 and demux by 4 modes will be compiled at some point in the near future.
    • all modes for the Roach1
    • The yellow block does, in general, almost nothing automatically. It's up to external code to suitably instruct the block to do what is required.
    • Upon power up the ADC ICs are in an undefined state. Yellow Block functions as well as user level Ruby scripts are available for the user to call to put the ADC ICs into the required mode. See above for the links to get these utilities.
    • The yellow block supports virtually all sorts of operating modes. The user selects these by writing and running python (or Ruby or ...) scripts which use katcp and tcpborphserver3 (or 2) to set the ADC16 IC registers as required.
  • There will be some number of bells and whistles that might optimize performance, say by changing some analog programmable gain on some input branch, that will be left to the user to perform or not.

Startup delay ambiguity

  • This ADC card has a "delay ambiguity" upon startup. It is due to a limitation of the Hittite HMCAD1511 chips.
  • These chips output pairs of their digital samples simultaneously over two high speed serial lanes, non-creatively named "A" and "B". The "first", "third", "fifth", etc. samples go out over lane A while the "second", "fourth", "sixth", etc. samples go out over lane B. The ordinal numbers in the previous sentence (e.g. "first") are in quotes because the "first" and subsequent samples are from the ADC chip's perspective after it "wakes up".
  • Within a single four channel ADC chip, there is never any delay ambiguity between the four channels. When multiple chips are used (such as the 4 chips on an ADC16 card) there is an inherent ambiguity as to whether samples corresponding to the same sample clock edge will appear in lane A or lane B.
  • For example, assume two chips have zero relative delay between their analog inputs and both start up at the exact same time such that they both take their "first" sample at t=0. The output samples S(t) would look like this:
    • ADC 0 Lane A: S(0), S(2), S(4), S(6), ...
    • ADC 0 Lane B: S(1), S(3), S(5), S(7), ...
    • ADC 1 Lane A: S(0), S(2), S(4), S(6), ...
    • ADC 1 Lane B: S(1), S(3), S(5), S(7), ...
  • On the other hand, assume that ADC 1 wakes up one sample period after ADC0. Then the outputs would look like this:
    • ADC 0 Lane A: S(0), S(2), S(4), S(6), ...
    • ADC 0 Lane B: S(1), S(3), S(5), S(7), ...
    • ADC 1 Lane A: S(1), S(3), S(5), S(7), ...
    • ADC 1 Lane B: S(2), S(4), S(6), S(8), ...
  • Any pair of corresponding S(t) samples are from the same ADC sample clock edge, but now it appears as if the signal into ADC 0 is delayed by one sample period relative to ADC 1, even though it really isn't.
  • The tests have not been performed to determine if the ADC "wakes up" when the ADC chip is physically powered up or software power cycled or software reset.
  • In either "wake up" scenario it would be very challenging to synchronize the startup of the 4 Hittite ADC chips on one ADC16 card to within better than one ADC sample period (e.g. better than 5 ns with 200 MHz sample clock). And it would be extremely challenging to do that across the 2 ADC16 cards on one ROACH2, and "impossible" to do that across multiple ROACH2s.
  • In short, this delay ambiguity is unavoidable and a post "wake up" calibration step is needed. Unfortunately, the Hittite ADCs do not provide any internal way to facilitate this calibration so it must be done by looking at the samples from correlated analog inputs. Whether those correlated analog inputs are the sky or a coupled-in common noise source that can be turned on for calibration is beyond the scope of the ADC16 card and gateware.

ADC16x250-8 coax rev 2 Inputs

  • Clock:
    • +6 dBm, 1.26 Vpeak_to_peak, sine wave into 50 ohm SMB jack (receptacle) connector.
    • Values down to 0 dBm are apt to be fine and is the minimum suggested input power level.
    • Values down at -3 dBm will incur an additional 6 dB in the phase noise of the on-board clock driver as well as reduced clocks at the ADC IC inputs.
    • Actual limits on the input clock level have not yet been measured in the lab. As discussed above and set by the limits of the Roach2 rev2's FPGA MMCM specifications the predicted limits are :

      • in 16 input mode: 67.5 to 120 MSPS (still TBD as of 2014mar08) and 135 to 240 MSPS.

      • in 8 input mode: 135 to 240 MSPS (still TBD as of 2014mar08) and 270 to 480 MSPS.

      • in 4 input mode: 270 to 480 MSPS (still TBD as of 2014mar08) and 540 to 960 MSPS

      • The ADC ICs have a programmable divider on the clock input. This divider can be 1,2,4 or 8. Thus, one could always supply a 960 MHz clock at the SMA input to the ADC16 board and then by changing this divider register select at run time the effective sample clock (240, 480 or 960 MHz) and the number of inputs/ADC IC (4 or 2 or 1) and thus one could switch between the 3 main modes without changing any cables.

      • At power up the ADC ICs are generally in the by-4 input mode. But this is not guaranteed. Depending on the system level clock distribution network and normal operating modes the max clock rate may be exceeded. No damage is expected. The current drawn from the 2.5 V rail can be significantly larger than in the operational state. Thus, the recommendation is to use the SPI interface to properly configure the ADCs into a mode compatible with the provided clock frequency.

    • 1:2 input clock balun. Different baluns may be used based on the degree of optimization for operation at a particular operating frequency. Or not.
    • 1:2 alternative input clock balun Mini-Circuits TC2-72T+ 10-700 MHz 1:2 input clock balun (PDF)
      • Note the typical output phases are within 3 degrees of 180 degrees apart from 1 to about 650 MHz.
      • These parts have not yet been tried on any board.
    • 1:1 alternative input clock balun. These parts have not been tested yet, as of 2013may29, but they general idea(hope?) is that the poor impedance match, due to the 1:1 rather than 1:2 ratio, won't cause significant problems. A serious investigation of drop in replacement parts that have 1:2 ratio and good specifications for 500-1000MHz hasn't been performed.
    • The one clock signal delivered to the board is received and then delivered to the 4 ADC IC chips via one low noise fanout buffer the Hittite Microwave HMC987LP5E
  • Analog Signals:
    • The full scale inputs to the Hittite ADC IC are (assuming single input into 50 ohm load)
      • AC coupled to (approximately) 650 MHz (typical)
      • 2 Vpeak_to_peak (+10 dBm) sine wave
      • -2.6 dBm gaussian noise w/ crest factor 6)
    • Due to the loss in the components just upstream of the ADC IC
      • the F3dB frequency of the board will be reduced, possibly considerably, relative to a Hittite ADC IC itself.
      • The full scale input level will be greater than that of the Hittite ADC IC itself.
      • See the testing section below for measured values.
      • The usable full scale range is also a function of the digital gain programmed into the ADC IC.
    • The actual ADC IC inputs are differential signals. This board has an AC coupled balun on each input to generate these differential signals. Each of the full scale differential inputs are :
      • -0.5 to +0.5 V (+4 dBm) sine wave
      • -8.5 gaussian noise w/ crest factor 6
      • centered around the around the ADC IC's Vcommon of AVDD/2 = c 1.8V/2 = 0.9V
      • with net input to the ADC IC pins of +0.4 to +1.4 V
    • The input circuitry, including balun and shunt caps, will be optimized for low frequency inputs (approx 4.5 MHz to 250 MHz). Different valued discrete components will need to be installed for optimal frequency response in different frequency ranges.
    • See for example the rev 2.1 BOM the PAPER project is using for its inputs.
    • the board will be populated with 16 50ohm coaxial cables terminated with bulkhead mount jack SMB connectors that pass thru custom holes in the 1U chassis and are mounted to a custom 1U faceplate.
  • Power:
    • Power is delivered via the ZDok+ connector from the Host FPGA board.
    • As of 2013apr16 no power measurements have been made.
    • The power measurements are apt to be the same as on the ADC16x250-8_RJ45_rev_1.
  • Control/Config
  • ADC16x250-8 coax rev 2
    • Many ZDok+ pins became available after testing with the ADC16x250-8_differential_rev_1 board and Roach2 rev1 and Roach2 rev 2 showed that the line clock (LCLK) from 1 and only 1 Hittite ADC IC, and sophisticated use of the Xilinx FPGA's run time programmable delay taps, was required to cleanly capture all the digital data bits.
    • The pin out of the ZDok+ was changed dramatically for the ADC16x250-8_coax_rev_2, ADC16x250-8_RJ45_rev_1 and ADC16x250-8_coax_rev_1 boards to locate the programming signals where they are first used rather than intersperse them as would happen if they were swapped in place of the no longer used Hittite ADC IC line and frame clock signals.
    • The control and configuration programming signals are A1..A4, C1..C4, D1..D4 and F1..F2. This list includes 8 spare signals.
    • Unlike the ADC16x250-8_differential_rev_1, there is no need for an extra 10x2 programming cable.
    • See page 3 of the rev 2 pin mapping summary file shown below.
  • LEDs
    • LEDs? the ADC16 doesn't need any stinking LEDs.

ADC16x250-8 coax rev 2 Additional Datasheets

ADC16x250-8 coax rev 2 Block Diagram and pin mappings

ADC16x250-8 coax rev 2 Design Files

  • ADC16x250-8 coax rev 2.1 Bill of Material (BOM)
    • 2013sepXX One of the first customers of this board, PAPER, has chosen to modify the Rparallel and Rseries at all the analog inputs to the ADC ICs to improve the S11 matching due to the 50+ feet of coax cable between the signal source and the ADC16 inputs.
    • there are 2 changes. line items #16 and #17 as found on the top of page 2 of the PDF. Those are the only 2 changes.
    • rev 2.1 Bill of Materials (PDF)

ADC16x250-8 coax rev 2 Photos

blank circuit board

assembled circuit board

reworked circuit board

  • what rework ?
  • The PAPER project chose to rework in a 3dB attenuator, via small resistors, at the input to each analog input balun to improve the S11 matching due to the 57 ft or so of cable between the ADC and the module supplying the analog signal.

ADC16x250-8 coax rev 2 Test results

  • The performance of the coax rev 2 board is intended to be better in channel isolation and gain versus frequency when compared against the ADC16x250-8_coax_rev_1 and ADC16x250-8_differential_rev_1 boards.
  • Until tests are run on the coax rev 2 boards please see the test results sections of ADC16x250-8_coax_rev_1 and ADC16x250-8_differential_rev_1
  • Perhaps the most interesting results will be found at ADC16_cross_corr_tests
  • [ADC rms counts versus test tone frequency (PDF)]
  • [band limited noise dBm to ADC rms counts (TXT)]
    • The boards built for PAPER, specifically PSA256 as installed in the fall of 2013, have a 3 dB pad reworked at the balun input. These are tested with the ADC IC digital gain set to 2 and a 100-200 MHz band of noise at -3.9 dBm and produce ADC rms counts of 12.4 or so.
  • network analyzer tests of the standalone SMB connector from the face plate to the PCB prior to installation. (PDF)
  • network analyzer tests of the 2 meter long LMR100A SMA-SMB cable some applications use to feed the SMB connector at the face plate (PDF)
  • allan variance test which measures the total power of a noise source as a function of time, and see where the measurements cease to improve with sqrt(time). 2013may29 TBD.
  • spectral allan variance test which measures the ratio of one tone to another, and see where that ratio measurement stops improving with sqrt(time). 2013may29 TBD.
  • PAPER tests
    • analog input is roughly 100 - 200 MHz with 200 MHz clock.
    • PAPER test #1 uses an analog input which switches back and forth between two noise sources of known power levels approximately 3 dB apart and record the measured ratio of these two power levels as a function of time. 2013may29 TBD.
    • PAPER test #2 uses an analog input of some sort with known passband stability and record how the measured spectral bumps change over time. 2013may29 TBD.
  • generic tests
    • as above but in 4 input mode and wider bandwidth test signals.
    • test the basics with Roach2 rev2, Roach2 rev1 and Roach1 hosts.
    • wide bandwidth input with deep analog notch filter and measure amount of notch filled in.
    • IEEE Std 1241-2000

1U Enclosure changes

Please see the ADC16x250-8 coax section near the bottom of the ROACH 2 Enclosure wiki page.

Contributors

  • Dan Werthimer
  • Aaron Parsons
  • Dave DeBoer
  • Calvin Cheng
  • Matt Dexter
  • design reviews generously provided by many of the CASPER community
  • Jama Mohamed
  • Glenn Jones
  • David MacMahon
  • Zaki Ali

ADC16x250-8 coax rev 2 Inventory as of 2013sep19

  • 40 bare boards have been purchased.
  • 40 bare boards have been fabricated.
  • 1 board has been assembled by RAL; More than 24 boards have been assembled by DigiCom.
  • about 20 boards have been tested in the lab; digital tests AOK; analog tests ongoing

Schedule

Here's a somewhat randomly selected dates of possible significance.

  • 2013may07 ADC16x250-8_coax_rev_1 crosscorrelation results have been reviewed and found to be a bit disappointing; a coax rev 2 board will be made. The primary change will be to space apart the baluns as much as possible, even those on opposite sides of the PCB. Test results show the balun to balun coupling is stronger than that of the differential traces between the balun and the ADC IC.
  • 2013may12 after more lab tests we may be measuring the limit of the ADC IC. It seems that there is significant coupling upstream of the analog input crossbar and somewhere downstream of the Rseries portion of the analog input subcircuit. Perhaps the ADC IC package and die at the internal track and hold receiver circuit ?
  • 2013may24 after a detour to release the ADC16x250-8_RJ45_rev_1 board the coax rev 2 board is at the board fab house.
  • 2013jun10 is the target date for RAL to start to assemble the first coax rev 2 board
  • 2013jun11 first board was assembled
  • 2013jun12 the first board is fully assembled, inspected and started the lab test phase; everything tried is AOK.
  • 2013jun18 RFQ for assembly run of 19 units submitted
  • 2013jun18 start testing with all 16 analog input SMB coax cables
  • 2013sep19 PAPER is switching its boards from rev 2 BOM to rev 2.1 BOM for improved S11
  • 2013nov20 16 of these boards are installed in the Karoo as the PAPER PSA128 F Engines. Two per Roach2 rev2 for 32 input F Engines.
  • 2014mar01 4 of these boards, customized for just 4 analog inputs, are installed at Arecibo as the SERENDIP6/ALFABURST F Engines.
  • 2014mar08 long overdue round of wiki edits for clarifications, new photos, ...
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