Page Index - riscvarchive/riscv-CMOs-discuss GitHub Wiki
89 page(s) in this GitHub Wiki:
- Home
- new riscv-CMOs-discuss/wiki/Home.md
- RISC-V standard disclaimer
- RISC-V CMO proposal
- Arguments, Counter-Proposals, etc.
- Wiki TC of Pages
- Wiki Administrivia
- Non-CMO stuff to be deleted
- ======================================TOC spacer
- Actual CMO Operations
- Administrivia
- Administrivia CMOS TG
- Agenda for CMOs TG
- An even quicker and dirtier summary of proposed instruction encodings for RISC V CMOs
- Arguments against address range CMO.AR
- Block memory operations such as MEMSET and MEMCOPY
- CBO.UX vs CMO.ALL vs CMO.UR.asciidoc
- CMO goals
- CMO operation list for encodings
- cmo_type CMO instruction flavor
- CMOs (Cache Management Operations)
- CMOs cut across many fields
- CMOs Not Based on Memory Address
- CMOs proportional to cache size rather than address range
- CMOs proposal
- CMOs WG Draft Proposed Charter
- convenient short names for examples
- draft actual CMO operations
- draft CMO domains and levels
- draft CMO instruction formats
- draft CMO issues
- Draft CMO proposals
- draft CMO type spreadsheet
- draft Fixed Block Size Prefetches and CMOs
- draft Microarchitecture Cache Index CMO.UR CBO.UX
- draft microarchitecture timing state flushes
- draft Privilege for CMOs
- draft Variable Address Range CMOs
- Example: Config WG charter
- Examples of other Working Group charters
- Extended CMO types
- Fixed Block Size Prefetches and CMOs
- generated HTML and PDF for CMOs proposal
- hack relative URLs in github project wiki repo
- How to search this wiki, repo, issues, etc.
- I am frustrated that we are going around in circles with respect to modulation of CMOs
- in band tagging pointers
- Instructions that Support Partial Progress
- interception, modulation, and mapping of CMOs
- ISSUE process migration argues for whole cache invalidation operations and against the partial progress loop construct
- Mailing lists interested in CMOs
- Mandatory versus Optional CMOs, PREFETCHES, and CPHs
- Meeting 11 09 2020
- microarchitecture range loop
- Microarchitecture Structure Range CMOs
- Motivation for Address Range CMO.AR
- No data value dependent exceptions for RISC V
- Non CMO stuff to be deleted
- Non temporal loads vs CMOs in loops
- Overview of CMO operations
- Privilege for CMOs
- Problems editing GitHub wiki using speech recognition
- Process migration while performing multiple cache block operations together
- Quantization, dequantization, and interpolation instructions for DL, math, etc.
- Quick and dirty list of Actual CMOs
- Quick and Dirty Proposal for RISC V CMOs
- Ri5 CMOs proposal
- RISC V CMO proposal
- RISC V needs CMOs, and hence a CMO Working Group
- RISC V standard disclaimer
- Sectored Cache Terminology
- Semantics of Whole Cache Flushes CMO.ALL
- Semantics of Whole Cache Flushes CMO.ALL with Process Migration
- Sharing Drawings and Diagrams
- SourceDest to support Exception Transparency
- STATUS almost done maybe
- techpubs
- techpubs info
- Terminology for instructions that manage microarchitecture state such as caches, prefetchers and predictors
- terminology notation
- TOC Table of Contents
- Variable Address Range CMOs
- Variable Address Range Instructions like CMOs, MEMSET, MEMZERO, and MEMCOPY
- variable address range loop
- Virtual or Physical CMO instruction flavor
- voice typos editing this wiki
- Why CMOs.xlsx was written in Excel
- Wiki and Repo crosslink issues
- wiki stuff: Notes on GitHub wiki pages