Here is the RISC-V standard disclaimer

I am sending this as email, so that I can pin it to the top of our message archive. TBD: link.

I am also posting it on our wiki https://github.com/riscv/riscv-CMOs/wiki/RISC-V-standard-disclaimer

I will post or link to it from our meeting announcements and agendae. TBD: link.

-------- Forwarded Message --------

Subject: 	[RISC-V] [tech-chairs] disclaimer slides to add to your group meeting agendas
Date: 	Mon, 28 Sep 2020 09:12:25 -0700
From: 	mark <[email protected]>
To: 	chairs <[email protected]>, tsc <[email protected]>


https://drive.google.com/file/d/1FmXDqa20NNjtfFyPdcT7__-AfO7ke9J_/view?usp=sharing

Because I am a bit obsessive about this sort of thing, I will here extract the text of this disclaimer. However, note that this extracted text may be obsoleted if the disclaimer in an official place is edited, so please refer to the Google Drive link if necessary, and to any other official place it may be moved to in the future. NOTE: Google search did not find this for me (Does Google search ever index Google Drive?), but did return similar documents Such as those whose URLs are in the below:

Antitrust Policy Notice

RISC-V International meetings involve participation by industry competitors, and it is the intention of RISC-V International to conduct all its activities in accordance with applicable antitrust and competition laws. It is therefore extremely important that attendees adhere to meeting agendas, and be aware of, and not participate in, any activities that are prohibited under applicable US state, federal or foreign antitrust and competition laws.

Examples of types of actions that are prohibited at RISC-V International meetings and in connection with RISC-V International activities are described in the RISC-V International Regulations Article 7 available here: https://riscv.org/regulations/

If you have questions about these matters, please contact your company counsel.

RISC-V International

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

We are a transparent, collaborative community where all are welcomed, and all members are encouraged to participate.

We as members, contributors, and leaders pledge to make participation in our community a harassment-free experience for everyone.

https://riscv.org/risc-v-international-community-code-of-conduct/