SourceDest to support Exception Transparency - riscvarchive/riscv-CMOs-discuss GitHub Wiki
This instruction family is restartable after partial completion. E.g. on an exception such as a page fault or debug address breakpoint the output register RD is set to the data address of the exception, and since the instruction is source/dest, with the register numbers in RD and RS1 required to be the same, returning from the exception to the CMO.UR instruction will pick up execution where it left off.
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Note
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Rationale: source/dest by requiring RD=RS1
This proposal has chosen to implement source/dest by requiring separate register fields RD and RS1 to contain the same value. An alternative was to make register field RD both an input and an output, allowing RS1 and RS2 to be used for other inputs. Separate RD=RS1 source/dest is more natural for a RISC instruction decoder, and detecting RD=RS1 has already been performed for other RISC-V instructions, e.g. in the V extension. However separate RD=RS1 "wastes" instruction encodings by making RD!=RS1 illegal, and leaves no register free in the CMO.VAR instruction format for any 3rd operand such as the CMO type, hence requiring .<cmo_specifier> in the instruction encoding. TBD: see who cares about RD=RS1 source/dest? |