The github wiki apparently has online macros such as TOC (Table Of Contents) disabled.

That's okay, I've written TOCs for other wikis that operate offline. Not yet using here.

This just a baby first step: links extracted.

• TBD: hand edit to logical structure.
• TBD: delete non-TOC links
• TBD: collect non-linked / non-TOC'ed pages

===

Issues

Dang, no easy crosslinking between Github wiki and issues.

TBD: auto generate issue summaries

• not for all, but for important pending issues
• TBD: mark in the issue database?

Official GitHub repo issues:

• https://github.com/riscv/riscv-CMOs/issues/2

Original/personal issues:

• https://github.com/AndyGlew/Ri5-stuff/issues/2
  • Verify that the recommended partial instruction completion loop constructs for CMOs operate correctly if optional prefetches or hints are treated as NOPs. #2

  TBD: migrate pending issues from personal to official CMOs depository

===

TBD: this is badly out of datae - so out of date, it should be abandoned if the scripts are not rerun soon. 2020-08-12

• An-even-quicker-and-dirtier-summary-of-proposed-instruction-encodings-for-RISC-V-CMOs
  • Fixed Block Size Prefetches and CMOs
• Block-memory-operations:-such-as-MEMSET-and-MEMCOPY
  • C library block memory operations
  • exception transparency for instructions with partial completion
  • partial completion
• CMO-goals
• CMOs-(Cache-Management-Operations)
  • An even quicker and dirtier summary of proposed instruction encodings for RISC-V CMOs
  • CMO-types issue
  • Consensus Work in Progress
  • Fixed Block Size Prefetches and CMOs
  • Instruction Name Choice
  • Non-Address Based CMOs for Abstraction and Efficiency
  • Overview of CMO operations
  • Quick and Dirty Proposal for RISC-V CMOs
  • STATUS: almost done? - maybe
  • Terminology for instructions that manage microarchitecture state such as caches, prefetchers and predictors
  • Variable Address Range CMOs
• CMOs-Not-Based-on-Memory-Address
  • bulk invalidate
• CMOs-proportional-to-cache-size-rather-than-address-range
  • CMOs based on cache microarchitecture
• Extended-CMO-types
• Fixed-Block-Size-Prefetches-and-CMOs
  • An even quicker and dirtier summary of proposed instruction encodings for RISC-V CMOs
  • Extended CMO Type
  • Mnemonics and Names
  • STATUS: almost done - maybe
• Home
  • CMOs (Cache Management Operations)
  • Quantization, dequantization, and interpolation instructions for DL, math, etc.
  • Sharing Drawings and Diagrams
  • hack-relative-URLs-in-github-project-wiki-repo
• ISSUE:-process-migration-argues-for-whole-cache-invalidation-operations-and-against-the-partial-progress-loop-construct
  • CMO.UR loop construct
  • parent page
• Instructions-that-Support-Partial-Progress
• Mandatory-versus-Optional-CMOs,-PREFETCHES,-and-CPHs
  • <cmo_type>
• Non-Address-Based-CMOs-for-Abstraction-and-Efficiency
  • (see issue)
  • CMO UR descriptor operand
  • CMO UR index
  • CMO descriptor
  • CMO loop construct
  • CMO.UR loop construct
  • Instructions that Support Partial Progress
  • RISC-V hardware error reporting
  • machine check
  • system description such as CPUID or config string
  • trap or use for other instructions
• Overview-of-CMO-operations
  • Survey of CMOs in Modern Computer Architectures
• Quantization,-dequantization,-and-interpolation-instructions--for-DL,-math,-etc.
  • multipart instruction approach
• Quick-and-Dirty-Proposal-for-RISC-V-CMOs
  • <cmo_type>
  • <virtual/physical>
  • CMO goals
  • CMO variable address range alternatives
  • CMOs Not Based on Memory Address
  • CMOs based on cache microarchitecture
  • CMOs proportional to cache size rather than address range
  • Instantaneous Flushes of Predictor and Cache State
  • Transparent Resumeability Prefers SrcDst Register Operands
  • full memory addressing mode rs1+imm12 for prefetches and CMOs
• STATUS:-almost-done - maybe
  • Proposal Status Tags
  • STATUS: almost done - maybe
• Sharing-Drawings-and-Diagrams
• Some-Page
• Terminology-for-instructions-that-manage-microarchitecture-state-such-as-caches,-prefetchers-and-predictors
  • At the time of writing pages in this document (wiki)
  • BTB
  • CMOs (Cache Management Operations)
  • CMOs-(Cache-Management-Operations)
  • CPH (Cache Performance Hints)
  • CPH (Cache Performance Hints) instructions
  • HWDS (Hardware Data Structure)
  • List of optional versus mandatory CMOs
  • Mandatory versus Optional CMOs, PREFETCHES, and CPHs
  • PREFETCH instructions
  • Performance Related Hardware Data Structure
  • Performance Related Hardware Data Structures
  • TLB
  • at the time of writing
  • branch predictor stew
  • cache push out or post-store
  • clean or flush
  • optional prefetches or post-store
  • pHWDS
  • partial instruction completion loop constructs
  • partial instruction completion
• Virtual-or-Physical-CMO-instruction-flavor
• cmo_type-CMO-instruction-flavor
  • <extended_cmo_types>
  • Point of Long Term Persistence
  • Point of Short Term Persistence
  • Point of Unification
  • Survey of CMOs in Modern Computer Architectures
• hack-relative-URLs-in-github-project-wiki-repo
  • ..
  • ../../wiki