Page Index - mbits-mirafra/computerArchitectureCourse GitHub Wiki

236 page(s) in this GitHub Wiki:

• Home
• Additional Concepts
• TEAM PROJECT : Designing a Simple RISCv Processor
• Batch 9 CA Summaries
• Adding beq and j Instruction
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• Adding Load and Store Instruction
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• Additional information on RARS simulator
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• Analysing Performance
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• Architecture Examples
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• Architecture Space
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• ARM Registers
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• AXI interface between register files and memory
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• Branch Instruction
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• CA Session 2 Summary
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• CA Session 3 Summary
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• CA Session 4 Summary
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• CA Session 5 Summary
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• CA Session 6 Summary
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• CA Session 7 Summary
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• CACHE HIT AND MISS
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• cache memory
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• Clocked State Elements
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• Constant Value in Hardware
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• Control Hazard
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• Control Inputs For Different Instructions
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• Converting HTTPS link to an SSH link
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• Data Hazards
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• Data Memory
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• Datapath and Control
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• Decoding machine Language
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• Difference between class and structure
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• Difference between import and `include
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• Different toolchains
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• Exact use of Write strobe and absence of Read strobe in AXI4
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• ExampleProgram
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• Guide for using RARS Simulator
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• History of Computers
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• HTTP vs SSH
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• Implementation using PLAs
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• Improving resources
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• Installation Steps for Windows
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• Instruction cycle
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• Instruction cycle ‐fetch, addressing, passing operands to ALU, incrementing PC
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• Instruction Set Architecture 1
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• Intel x86 Architecture
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• Introduction
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• Introduction of Instructions
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• Introduction to QTSPIM
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• Jump Instruction
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• Jump Register Instruction
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• Lecture 21
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• Lecture 4
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• Lecture 5 & 6
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• Lecture 7
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• Memory Hierarchy
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• Memory hierarchy ‐ 5
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• Memory hierarchy ‐3
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• Memory hierarchy ‐4
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• MIPS and RISC V Components
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• MIPS and RISCV Components
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• MIPS and RISCV Register files
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• MIPS Instruction
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• MIPS vs ARMv8
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• MIPS VS PowerPC
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• MIPS vs RISC
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• Miscellaneous Circuit elements
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• MOVE Instructions
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• Operations in ARMv8‐M
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• Operations in RISC V
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• Page Numbers & Videos Referred for Lecture 4
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• Page Numbers & Videos Referred for Videos 5&6
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• Part 2
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• part1
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• part3
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• Passing operands to ALU, Incrementing PC
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• Pipelining
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• Pipelining Hazards
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• pipelining&types
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• POINTER VS INDEX
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• Portable C
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• PowePC Architecture
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• PowePC Instructions
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• Power down techniques
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• PowerPC Architecture.
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• PowerPC Branch Instruction
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• PowerPC Registers
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• Problems with single cycle design
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• Procedural Abstraction
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• Processor Design
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• Processor design 5
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• Processor Design ‐ 6
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• Processor Design ‐2
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• Processor Design ‐3
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• Processor Design ‐4
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• Processor Design ‐5
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• Processor Design‐7
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• Program Memory
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• Pseudo Randomization
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• QTSPIM
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• REGISTER FILE AND PROGRAM MEMORY
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• Registers
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• RISC V Addressing
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• RISCV
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• RISCv vs ARMv8
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• RISC‐V SIMULATOR INSTALLATION
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• Seed Number
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• Session 8 Summary
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• Sorting Using Assembly Language
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• SPARC Architechture
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• SPARC Architecture
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• SPARC Instructions Formats
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• SPARC Registers
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• Structural Hazard
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• Sum of Array
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• Sum of Array elements
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• sum of arrays
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• Summary 8
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• Summary 8(b)
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• Team‐3 wiki
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• VAX Architecture
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