Operations in ARMv8‐M - mbits-mirafra/computerArchitectureCourse GitHub Wiki

Arithmetic Instructions

Instruction	Example	Meaning	Explanation
ADD	ADD R0, R1, R2	R0 = R1 + R2	Adds values in registers R1 and R2 and stores the result in R0
SUB	SUB R0, R1, R2	R0 = R1 - R2	Subtracts the value in register R2 from R1 and stores the result in R0
ADDS	ADDS R0, R1, #10	R0 = R1 + 10	Adds the immediate value 10 to the value in R1, stores result in R0; updates flags
SUBS	SUBS R0, R1, #10	R0 = R1 - 10	Subtracts the immediate value 10 from the value in R1, stores result in R0; updates flags
MUL	MUL R0, R1, R2	R0 = R1 * R2	Multiplies values in registers R1 and R2 and stores the result in R0
UDIV	UDIV R0, R1, R2	R0 = R1 / R2	Divides the unsigned value in R1 by the unsigned value in R2, stores quotient in R0
SDIV	SDIV R0, R1, R2	R0 = R1 / R2	Divides the signed value in R1 by the signed value in R2, stores quotient in R0
MLS	MLS R0, R1, R2, R3	R0 = R1 - (R2 * R3)	Multiplies R2 and R3, then subtracts the result from R1, and stores it in R0

Logical Instructions

Instruction	Example	Meaning	Explanation
AND	AND R0, R1, R2	R0 = R1 & R2	Bitwise AND of values in registers R1 and R2, result stored in R0
ORR	ORR R0, R1, R2	R0 = R1 | R2	Bitwise OR of values in registers R1 and R2, result stored in R0
EOR	EOR R0, R1, R2	R0 = R1 ^ R2	Bitwise XOR of values in registers R1 and R2, result stored in R0
BIC	BIC R0, R1, R2	R0 = R1 & ~R2	Bitwise AND of value in R1 with the complement of the value in R2
ANDS	ANDS R0, R1, #100	R0 = R1 & 100	Bitwise AND of value in register R1 and immediate value 100; updates flags
LSL	LSL R0, R1, #2	R0 = R1 << 2	Logical left shift of the bits in register R1 by 2 positions
LSR	LSR R0, R1, #2	R0 = R1 >> 2	Logical right shift of the bits in register R1 by 2 positions
ROR	ROR R0, R1, #2	R0 = R1 ROR 2	Rotate the bits in register R1 right by 2 positions

Data Transfer Instructions

Instruction	Example	Meaning	Explanation
LDR	LDR R0, [R1]	R0 = [R1]	Loads the value from the memory address in R1 into R0
STR	STR R0, [R1]	[R1] = R0	Stores the value in R0 into the memory address in R1
LDRB	LDRB R0, [R1]	R0 = [R1]	Loads an 8-bit byte from the memory address in R1 into the least significant byte of R0
STRB	STRB R0, [R1]	[R1] = R0	Stores the least significant byte of R0 into the memory address in R1
LDRH	LDRH R0, [R1]	R0 = [R1]	Loads a 16-bit halfword from the memory address in R1 into R0
STRH	STRH R0, [R1]	[R1] = R0	Stores the least significant 16 bits of R0 into the memory address in R1
LDM	LDM R0, {R1, R2}	R1 = [R0], R2 = [R0+4]	Loads multiple registers starting from the memory address in R0
STM	STM R0, {R1, R2}	[R0] = R1, [R0+4] = R2	Stores multiple registers starting from the memory address in R0
LDRSB	LDRSB R0, [R1]	R0 = sign-extend([R1])	Loads an 8-bit byte from memory address in R1, sign-extends it to 32 bits, and stores in R0
LDRSH	LDRSH R0, [R1]	R0 = sign-extend([R1])	Loads a 16-bit halfword from memory address in R1, sign-extends it to 32 bits, and stores in R0

Conditional Branch Instructions

Instruction	Example	Meaning	Explanation
BEQ	BEQ label	Branch if equal	Branches to the label if the zero flag (Z) is set.
BNE	BNE label	Branch if not equal	Branches to the label if the zero flag (Z) is clear.
BPL	BPL label	Branch if positive or zero	Branches if the negative flag (N) is clear.
BHI	BHI label	Branch if higher	Branches if the carry flag (C) is set and the zero flag (Z) is clear.
BLS	BLS label	Branch if lower or same	Branches if the carry flag (C) is clear or the zero flag (Z) is set.
BGE	BGE label	Branch if greater or equal	Branches if the negative flag (N) equals the overflow flag (V).
BLT	BLT label	Branch if less than	Branches if the negative flag (N) does not equal the overflow flag (V).
BGT	BGT label	Branch if greater than	Branches if the zero flag (Z) is clear and the negative flag (N) equals the overflow flag (V).
BLE	BLE label	Branch if less or equal	Branches if the zero flag (Z) is set or the negative flag (N) does not equal the overflow flag (V).