PowerPC Registers - mbits-mirafra/computerArchitectureCourse GitHub Wiki

PowerPC Registers are:

  1. General-Purpose Registers(GPR).
  2. Floating-point registers(FPR).
  3. Condition Register(CR).
  4. Floating-Point Status and Control Register (FPSCR).
  5. Fixed-Point Exception Register (XER).
  6. Link Register(LR).
  7. Count Register (CTR).

powerPc

General-Purpose Registers(GPR):

The general-purpose register file consists of 32 GPRs designated as GPR0–GPR31.

  • Source and destination for all integer operations
  • address source for all load/store operations.
  • They also provide access to SPRs.
  • All GPRs are available for use with one exception: in certain instructions, GPR0 simply means the value 0, and no lookup is done for GPR0's contents.

register (1)

Floating-Point Registers(FPR):

  • 32 floating-point registers with 64-bit precision.
  • source and destination operands of all floating-point operations
  • can contain 32-bit and 64-bit signed and unsigned integer values, as well as singleprecision and double-precision floating-point values.
  • FPR's also provide access to the FPSCR(Floating-Point Status and Control Register)
  • FPSCR captures status and exceptions resulting from floating-point operations, and also provides control bits for enabling specific exception types.
  • Instructions to load and store double precision floating point numbers transfers 64-bit of data without conversion.
  • Instructions to load from memory single precision floating point numbers convert to double precision format before storing them in the register.

floating

Condition Register(CR):

The condition register (CR) is a 32-bit register that reflects the result of certain operations and provides a mechanism for testing and branching. The bits in the CR are grouped into eight 4-bit fields, CR0–CR7.

cr

Bit Description
0 Less than(LT)—This bit is set when the result is negative.
1 Greater than(GT)—This bit is set when the result is positive (and not zero).
2 Equal (EQ)—This bit is set when the result is zero.
3 Summary overflow (SO)—This is a copy of the final state of XER[SO] at the completion of the instruction.

In case of MIPS we have seen that there is an instruction slt which does comparison and the result is put in one of the general purpose registers. But in power PC and several other machines the result of instruction for example comparison or even arithmetic is put in special bits of a register or flags.

Floating-Point Status and Control Register (FPSCR):

  • FPSCR 32-bit register used to store the status and control of the floating-point operations.
  • Bits 0–23 are status bits.
  • Bits 24–31 are control bits.
  • Status bits in the FPSCR are updated at the completion of the instruction execution.

Fixed-Point Exception Register (XER):

  • The Fixed-Point Exception Register (XER)- used for indicating conditions for integer operations, such as carries and overflows.
  • The number of bytes to be transferred by the load/store string indexed instructions.

Link Register(LR):

  • LR contains the address to return to at the end of a function call.
  • LR is a special register where link addresses are stored and this has a double purpose not only for procedural linkages it can also be used for loops.

For example: when you are beginning the loop, with the help of the instruction you can have that beginning of the loop address stored in this register and at the end of the loop you can simply use this information to jump back so you do not need to specify explicitly the address but you can simply refer to link register so it is also used to jump back to the beginning of the loop.

Count Register (CTR):

  • CTR used to hold a loop count that can be decremented during the execution of branch instructions.
  • So there are special instructions which will allow this to be incremented decremented and tested so that facilitates execution of loop where the iterations are driven by a count.