Registers - mbits-mirafra/computerArchitectureCourse GitHub Wiki

RISC characteristics:

  • Less no.of addressing modes (either 1 or 2)
  • Register addressing
  • Memory addressing (load and store instructions)
  • Fixed length instructions which helps in scheduling while pipelining
  • Large no.of registers with register to register operations also some processors use register to memory operations.
  • In RISC instructions are simple so that they can be implemented directly with help of hardware

RISC-V has address space of 2^32 bytes for all memory accesses. Address space is circular,so that the byte at address 2^(32−1) is adjacent to the byte at address zero. Memory is byte-addressable.

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  • Each register is 32 bit wide.
  • Register x0 is hardwired to 0 and is used as target register when the result is to discarded or if 0 is required as the source.
  • x1-x31 are general purpose registers.
  • The 32bit integers they hold are interpreted,depending on the instruction that access the registers. (Examples:Boolean values,two’scomplement signed binary integer so run signed binary integers,stack pointer or return address).
  • RISC-V does not define a specific subroutine return address link register, but it does suggest that the standard software calling convention should use register x1 to store the return address on a call.
  • There is a Program Counter (PC) that holds the address of the current instruction. The PC cannot directly be written or read using load/store instructions.

Register usage conventions

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