Passing operands to ALU, Incrementing PC - mbits-mirafra/computerArchitectureCourse GitHub Wiki

Passing Operands to ALU:

Instruction Execution Cycle:

The cycle involves fetching instructions from memory, decoding them, executing them, and storing results back in memory or registers.

ALU Operations:

Two inputs (operands) are sent to the Arithmetic Logic Unit (ALU) for processing, resulting in an output. The ALU performs operations based on instructions, which are determined by opcode (bits 26 to 31) and function fields (bits 0 to 5).

Register File:

Outputs from the ALU are stored back into the register file. The register file has read and write ports. The output of the ALU goes back to the appropriate write port. The destination address (bits 11 to 15) specifies where the result should be written in the register file.

Incrementing PC:

PC (Program Counter) holds the address of the next instruction. After each instruction, PC needs to be updated to point to the next instruction. Incrementing PC typically involves adding a fixed value (e.g., 4) to its contents.

Clock Edge Triggering:

Transitions in the state of the register file are edge-triggered by the clock. At the edge of each clock cycle, new values are either read from or written to the register file.

Sequential Execution:

Instructions are executed sequentially, with the result of one instruction becoming input for the next. The cycle repeats for each instruction, ensuring the orderly execution of the program.

Incrementing PC:

Single-Cycle Instruction Execution:

In this design, each instruction is executed within a single clock cycle. The instruction fetch, decode, execute, and store phases all occur within this one cycle.

Adder for PC Increment:

An adder is used to increment the Program Counter (PC) by a fixed value (in this case, 4). The incremented value is then fed back into the PC, preparing it for the next instruction fetch.

Clock Cycle Timing:

Time is measured in terms of clock cycles rather than in nanoseconds. At each clock cycle, the processor performs one complete instruction execution.

Instruction Completion and PC Update:

At time t, the current instruction completes execution, storing its result in the register file. Simultaneously, the PC is updated with the address of the next instruction, ready for the next cycle.

Sequential Execution:

Instructions are executed sequentially, one after another, without any overlap in their execution phases. Each instruction is completed before the next one begins, maintaining the order of instruction execution.

CPI (Cycles Per Instruction):

In this design, the CPI is 1, meaning that each instruction takes exactly one clock cycle to execute. Unlike designs with higher CPI values, where instructions may take multiple cycles to execute, this design aims for simplicity and efficiency by completing instructions in a single cycle.