Page Index - Juniper/open-register-design-tool GitHub Wiki

57 page(s) in this GitHub Wiki:

• Home
• open register design tool
• Overview
• Building Ordt from source
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• Cpp Model Outputs
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• Decoder and child region interface options
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• Hierarchical decoder example
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• JSpec Output
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• Options affecting RTL structure
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• Ordt Control Parameters
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• Other Outputs
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• Python Model Output
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• Running Ordt
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• Running Ordt Tests
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• Source contributions
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• SystemRDL examples
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• SystemRDL Output
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• SystemVerilog IO descriptions
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• SystemVerilog Output
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• Using JSpec input
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• Using SystemRDL input
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• UVM Model Output
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• uvm_reg_block_rdl methods
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• uvm_reg_field_rdl methods
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• uvm_reg_field_rdl_counter methods
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• uvm_reg_field_rdl_interrupt methods
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• uvm_reg_rdl methods
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• uvm_vreg_rdl methods
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• Verilog Testbench Output
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• XML Output and Viewer Utility
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