SystemRDL examples - Juniper/open-register-design-tool GitHub Wiki
Some SystemRDL examples showing hw ports generated
Simple configuration registers
images/rdl_examples/basic_config.png
Hw writeable register
images/rdl_examples/hw_write.png
Basic interrupt register
images/rdl_examples/simple_intr.png
Interrupt with an enable
images/rdl_examples/enable_intr.png
Basic counter
images/rdl_examples/simple_cntr.png
