Ordt Control Parameters - Juniper/open-register-design-tool GitHub Wiki
Ordt provides a mechanism to pass in parameters to specify various code generation options (eg, base address of a block in context of the chip). Use of the –parms command line option will specify an input file containing parameters to be used for code generation. Multiple parameter files can be read using the –parms command line option multiple times. In addition, parameters can be specified in-line in an rdl input file by enclosing in <PARMS>, </PARMS> tags. An example parameters file is shown below (shows an example of each parameter, but all are optional).
// global parameters
global {
min_data_size = 32 // sets allowed register sizes range (min_data_size to 16*min_data_size)
base_address = 0x80000000 // block base address
use_js_address_alignment = true // align per jspec reg array and register_set rules
suppress_alignment_warnings = true // inhibit register/regfile base address alignment messages
default_base_map_name = "zz" // default address map name (replaces 'default_name' in cases where no addrmap is specified)
allow_unordered_addresses = true // attempt to correct order of elements defined in non-descending order
}
// jspec input parameters
input jspec {
root_regset_is_addrmap = true // root component will be created as an addrmap rather than a regfile/regset (not if typedef)
process_typedef = "typedef_name" // process this typedef
}
// rdl input parameters
input rdl {
process_component = "comp_name" // process this component
resolve_reg_category = true // try to determine category from rdl properties if not specified
restrict_defined_property_names = true // user defined rdl properties should always start with 'p_'
default_rw_hw_access = true // default field hw access is rw rather than r
}
// systemverilog output parameters
output systemverilog {
leaf_address_size = 40 // leaf address bits
root_decoder_interface = ring16 // parallel | leaf | serial8 | ring8 | ring16 | ring32
secondary_decoder_interface = serial8 // none | parallel | serial8 | ring8 | ring16 | ring32 | engine1
secondary_base_address = 0x40 // base address as viewed by secondary decoder interface
secondary_low_address = 0x50 // low valid address on secondary decoder interfaces
secondary_high_address = 0x5f // high valid address on secondary decoder interfaces
secondary_on_child_addrmaps = true // add secondary interface to child decoders also
base_addr_is_parameter = false // base address parameter will be added to top module
module_tag = "_version1" // tag to be added to generated module names
use_gated_logic_clock = false // use separate gated clock for registers
block_select_mode = always // how is block select generated (internal | external | always)
export_start_end = true // create addr_start, addr_end outputs for this decoder
always_generate_iwrap = false // create int wrapper mod even if none specified in rdl
suppress_no_reset_warnings = true // inhibit field no reset messages
generate_child_addrmaps = false // generate child address maps
ring_inter_node_delay = 2 // delay stages to be added between generated decoders using ring interface type
bbv5_timeout_input = true // add input port(s) for bb root interface timeout
include_default_coverage = true // include default cover points in rtl
pulse_intr_on_clear = true // pulse interrupt output low if any child in intr tree is cleared
reuse_iwrap_structures = true // reuse similar interface/struct definitions in iwrap
optimize_parallel_externals = true // eliminate nack/size/r/w io where possible in parallel external intfs
use_async_resets = true // registers will use asynchronous reset
nack_partial_writes = true // issue nack for writes of size less than target
write_enable_size = 0 // size of data affected by each write enable in bits
max_internal_reg_reps = 4096 // maximum allowed replications allowed on an internal register
wrapper_info {
add_sync_stages "*swmod_o" 1 // add 1 sync delay stage to these IOs (use default clock)
//add_sync_stages "*_o" 2 newClk // add 2 stage syncronizer to these IOs using new clock
//add_sync_stages "*_o" 2 newClk mySyncModule // add 2 stage syncronizer to these outputs w/ new clock and module override
set_passthru "some_io" // set this wrapper IO to direct passthrough (default)
set_invert "some_other_io" // set this wrapper IO to invert
}
separate_iwrap_encap_files = true // generate a separate file for each wrap encap (interface/struct) type
generate_dv_bind_modules = true // if true generate diagnostic dv bind modules
use_global_dv_bind_controls = true // if true diagnostic dv bind module settings will be controlled by global packages
include_addr_monitor = true // generate io to monitor decoder transactions to a specified address range
generate_iwrap_xform_modules = false // generate common wrapper transform modules
}
// jspec output parameters
output jspec {
root_regset_is_instanced = true // instance the root or make it a typedef?
add_js_include = "/dir/foo.bar" // add an include for this file in jspec output
root_typedef_name="new_typedef" // override name of root typedef
root_instance_name="new_instance" // override name of root instance
root_instance_repeat=3 // override repeat count in root instance
add_user_param_defines = true // add user-defined parameter defines to the output
keep_fset_hierarchy = true // include fieldset hierarchy in output
}
// rdl output parameters
output rdl {
root_component_is_instanced = true // instance the root addrmap/regset or make it a comp definition (not if multi-typedef)?
output_jspec_attributes = true // pass attribute definitions from jspec input as-is
no_root_enum_defs = true // do not output any enum components defined at root level
}
// reglist output parameters
output reglist {
display_external_regs = true // include external regs in output?
show_reg_type = true // show int/ext type for each reg?
match_instance = "inst_name" // show only regs with matching instance names
show_fields = true // show field info for each reg
}
// uvmregs output parameters
output uvmregs {
is_mem_threshold = 512 // make replicated regs uvm_mem if reps greater-equal to threshold
suppress_no_category_warnings = true // inhibit reg has no category messages
include_address_coverage = true // include address coverage in model
max_reg_coverage_bins = 64 // limit address coverage bins for replicated regs
reuse_uvm_classes = true // allow reuse of register and block classes in model
skip_no_reset_db_update = false // bypass uvm_resource_db update for fields with no reset
uvm_model_mode = translate1 // set uvm model type (heavy | lite1 | native)
regs_use_factory = true // registers will be created by and registered with the factory
use_numeric_uvm_class_names = false // block and reg class names will use unique int rather than catenated path
uvm_mem_strategy = mimic_reg_api // set uvm_mem modeling strategy (basic | block_wrapped | mimic_reg_api)
base_address_override = 0x82000000 // model base address override
use_module_path_defines = true // use defines for setting root module paths
}
// xml output parameters
output xml {
include_field_hw_info = true // include field hw characteristics
}
// cheader output parameters
output cheader {
generate_memory_map = true // generate an enum containing register addresses
generate_bitfield = true // generate macros for extracting each register field
generate_explicit_functions = true // add bits.h contents inline rather then using include
}
annotate {
set_regset_property default uvmreg_prune = "true" components "assist_engine_1" // set default parameter on all matching register sets
set_reg_property cppmod_prune = "true" instances "foo.bar.*" // set parameter on all matching registers
set_field_property cppmod_prune = "true" instances "field_name" // set parameter on all matching fields
}
min_data_size (type=int, default=32): minimum allowed register width in bits. Defines the allowed range of register sizes (min_data_size to min_data_size*16). min_data_size defines the base word size that will be used for decoder transactions - byte address lsbs below this size will be discarded.
base_address (type=address, default=0x0): base address whose upper bits will be used to determine if the address sent to the rdl generated decoder is valid. A compare with this address will generate the accept/reject signals returned to the leaf (unlike the jspec generated code, an address matching the base address but not matching a decoder address will NOT generate reject to the leaf - rdl generated code will generate accept and return a nack in this case). The base address will also be passed to the generated uvm model.
use_js_address_alignment (type=boolean, default=true): align addresses per jspec register and register_set rules.
suppress_alignment_warnings (type=boolean, default=false): inhibit register/regfile base address alignment warning messages. If false, ordt will generate a warning if a register/regfile base address is shifted to meet alignment requirements.
default_base_map_name (type=string, default=’default name’): default address map name to be used in cases where no root address map instance name is specified (replaces 'default_name' in these cases).
allow_unordered_addresses (type=boolean, default=false): If true, ordt will allow registers/regfile instances to be specified with out of order base addresses within a regfile specification. If false, an error will be generated by the tool if a non-ascending base address is encountered.
root_regset_is_addrmap (type=boolean, default=false): if true, the root jspec register_set being read will be considered to be an rdl addrmap, rather than a regfile. This parameter will be ignored if multiple process_typedef parameters are specified.
process_typedef (type=string, default=null): Ordt assumes an instanced root level in jspec input files by default. If only specific typedefs are needed from the input jspec file, this parameter will indicate a root level typedef to be processed by ordt. Multiple process_typedef statements can be provided to convert several jspec typedefs to rdl. Use of multiple process_typedef parameters is not intended for generation of ordt output types other than rdl.
process_component (type=string, default=null): Similar to the process_typedef property for jspec, allows only rdl root level components having the specified name to be processed.
resolve_reg_category (type=boolean, default=true): assign register categories from rdl properties if not specified.
restrict_defined_property_names (type=boolean, default=true): if true, user defined rdl property names will be restricted to start with 'p_'. This eases identification of user properties and helps avoid name collisions in generated output.
default_rw_hw_access (type=boolean, default=false, added 170714.01): if true, default field hw access will be rw rather than r
* these parameters also apply to verilog output
root_decoder_interface (value=[parallel|parallel_pulsed|leaf|serial8|ring8/16/32], default=leaf): specifies the processor interface of the generated root decoder module. By default, the generated interface will be leaf type. The parallel type provides a generic parallel data read/write interface that is compatible with the default external(PARALLEL) interface that can be specified on regions within a parent decoder. The serial8 mode generates a narrow 8 bit data interface that is compatible with the external(SERIAL8) interface that can be specified on register regions of a parent decoder. The ring8/16/32 modes generate a 8/16/32 bit data interface that supports multiple client decoders attached as a ring. The ring8/16/32 modes are compatible with their corresponding external(RING8/16/32_Dn) interface types that can be specified on a parent decoder. The parallel_pulsed option (added in 180201.01) provides the same interfaces as parallel, except that read/write activation signals are a single high pulse rather than an active high level that deasserts upon ack/nack return.
secondary_decoder_interface (value=[none|parallel|parallel_pulsed|serial8|ring8/16/32|engine1], default=none): specifies the secondary processor interface of the generated root decoder module. The parallel_pulsed option (added in 180201.01) provides the same interfaces as parallel, except that read/write activation signals are a single high pulse rather than an active high level that deasserts upon ack/nack return.
secondary_base_address (type=address, default=null): specifies the base address as viewed by the secondary decoder interface.
secondary_low_address (type=address, default=null): specifies the low valid address on secondary decoder interfaces. Accesses to addresses below this value will result in a nack response.
secondary_high_address (type=address, default=null): specifies the high valid address on secondary decoder interfaces. Accesses to addresses above this value will result in a nack response.
secondary_on_child_addrmaps (type=boolean, default=false): if true, secondary uP interfaces will be added to generated child decoders also. By default, the secondary interface is only added to the root decoder.
base_addr_is_parameter (type=boolean, default=false): if true, an input parameter controlling block base address will be added to generated root and decoder modules. This parameter is only valid when decoder type is leaf or ring16, where these interface protocols allow multiple destination nodes and thus require additional address information (a unique base address) to identify each node. If false, the value of the global base_address parameter will be assigned directly in the generated RTL.
leaf_address_size (type=int, default=40): number of bits in the address sent from leaf to rdl generated decoder. This parameter is only valid when decoder type is leaf.
block_select_mode (value=[internal|external|always], default=external): if internal, block select indication will be generated inside the decode module, and output via a module IO. If external, one or more block select inputs will be added to pio module IO and ORed within the decoder to gate valid transactions. The number of block_select inputs will correspond to the number of addr_start/addr_end pairs generated. If always is specified, no block_select IO will be created and all transactions to the decoder will be assumed to be valid. This parameter is only valid when decoder type is leaf.
export_start_end (type=boolean, default=false): if true, addr_start|addr_end outputs will be generated for connection to the leaf block (non-macro blocks). If no external_decode structures are specified, a single start/end pair will be created. This parameter is only valid when decoder type is leaf.
use_gated_logic_clock (type=boolean, default=false): if true, a separate clock input (gclk) will be added to generated modules providing gated clock control of register logic. Generated decode modules will still use the ungated clock input (uclk) and will also provide a clock enable output that is activated upon module access and can be used to control an external clock gate for gclk. Note that control of gated clock logic in any address regions specified as external must be handled by the designer so that responses are generated correctly.
gated_logic_access_delay (type=int, default=5): if use_gated_logic_clock is specified, incoming read/write transactions will be delayed internally by the specified number of clock cycles. Intent of this delay is to allow clocks from external clock gate controlled by the decoder to stabilize before driving register logic.
suppress_no_reset_warnings (type=boolean, default=false): inhibit warning messages for fields that have no reset value assigned.
generate_child_addrmaps (type=boolean, default=false): If true, systemverilog modules will be generated for all addrmaps specified in the rdl hierarchy, even those in external regions. If false, only the root module containing decoder/logic rtl will be created. Child addrmaps in an external(BBV5_16) region will be generated with processor interface type of leaf to facilitate connection of child modules via a bbv5 ring. Child addrmaps in external(SERIAL8) or external(RING8/16/32) regions will be generated with interface types of serial8 and ring8/16/32, respectively, to allow direct connection of cascaded maps. Child addrmaps without an external designation or in an external(PARALLEL) region will be generated with interface type of parallel to allow direct connection of cascaded maps.
ring_inter_node_delay (type=int, default=0): specifies the number of delay stages to be added between generated ring attached decoders. This parameter is only valid when generating decoders of type ring8, ring16, or ring32.
bbv5_timeout_input (type=boolean, default=false): if true, a 12b input port(s) is added to the driving module for each region specified as external(BBV5_16). This allows bbv5 ring transaction timeouts to be set via RTL or a configuration field.
include_default_coverage (type=boolean, default=true): if true, toggle cover points will be added to the rtl for each interrupt and counter increment/decrement input pin in the generated register module.
pulse_intr_on_clear (type=boolean, default=false): if true, generated interrupt output signals will pulse low for a single cycle if any child interrupt in its intr tree is cleared.
optimize_parallel_externals (type=boolean, default=false, added 170504.01): if true, logic will be added to eliminate nack/size/r/w IO of external register regions specified as PARALLEL type. The optimization will only occur for regions containing a set of same-sized registers with no address gaps between registers. In these cases, nack of out of range address accesses, read of WO, and write of RO will be handled internally.
use_async_resets (type=boolean, default=false, added 170504.01): if true, generated registers will use asynchronous resets.
nack_partial_writes (type=boolean, default=false, added 170725.01): if true, writes of word size size less than the target register will result in a nack. By default, such transactions are ack'd and rely on validation of the returned size by the controller for detection. No changes are made to internal register state when a partial write occurs.
write_enable_size (type=int, default=0, added 170727.01): if non-zero, write enable inputs will be added to the decoder such that every write_enable_size bit slice of the write data is restricted to only allow write modifications when its corresponding enable is set. Enable inputs are only generated if either the primary or secondary decoder interface type is parallel.
max_internal_reg_reps (type=int, default=4096, added 170913.01): Sets the maximum allowed replications for an internal register. Depending on target technology for the generated rtl, large internal register replication counts can result in in efficient use of die area and decoder timing issues (typically large register arrays are handled using sram in an external space).
always_generate_iwrap (type= boolean, default= false): By default, a wrapper module creating systemverilog interface or struct encapsulations will only be created if the use_interface or use_struct properties are specified in rdl. Setting this property true will always create the wrapper module regardless of specified rdl properties.
reuse_iwrap_structures (type=boolean, default=false): if true, only unique interface/struct definitions will be generated and these will be reused as appropriate in the generated iwrap module. Unique structures will be named using their component name (if it exists and results in a unique structure in the output) - otherwise, the structure will be named using its instance path. By default, new structure definitions are generated for each rdl instance having use_new_interface or use_new_struct specified, even if some are equivalent.
wrapper_info (added 171011.01): If a wrapper info section is added in the control parameters, a wrapper module will be created that provides simple IO transforms as specified. Currently supported commands are:
add_sync_stages <io_name_pattern> <num_stages> <optional_clock> <optional_module> // add <num_stages> sync stages to specified wrapper IO
set_passthru <io_name_pattern> // set specified wrapper IO to direct passthrough (default)
set_invert <io_name_pattern> // set specified wrapper IO to invert
separate_iwrap_encap_files (type=boolean, default=false, added 180201.01): if true, a separate file will be generated for each encapsulation definition (interface or struct) that is used in the wrapper module. By default, these defines are included in the wrapper output file.
generate_dv_bind_modules (type=boolean, default=false, added 180201.01): if true, design-specific systemverilog modules will be generated that are can be bound to the auto-generated decoder and/or logic modules for design verification. Currently, an interrupt diagnostic module (causes assertions to fire when interrupt leaf fields activate) and a coverage module (adds coverpoints for interrupt input signals and counter incr/decr input signals if include_default_coverage is set, and toggle coverage of any field having the rtl_coverage property set) are generated.
use_global_dv_bind_controls (type=boolean, default=false, added 180201.01): if specified, the generated dv bind module behavior will be controlled by variables in a global package, ordt_dv_bind_controls.
include_addr_monitor (type=boolean, default=false, added 180502.01): if specified, address high and low inputs will be added to the generated decoder rtl allowing all transactions in a range of addresses to be detected. Four output signals providing single pulse indication of ack, nack, read, and write are provided.
generate_iwrap_xform_modules (type=boolean, default=true, added 180712.01): if false, inhibits generation of common module defines used in wrapper module transforms (these are generated/instanced when using certain wrapper_info commands).
root_regset_is_instanced (type=boolean, default=true): if false, the root jspec register_set will be output as a typedef rather than an instance.
add_js_include (type=string, default=null): if specified, a #include of the given file will be added to jspec output. Multiple add_js_includes are allowed.
root_typedef_name (type=string, default=null, added 171024.01): if specified, this string will specify the name of the root typedef in the output.
root_instance_name (type=string, default=null, added 171024.01): if specified, this string will specify the name of the root instance in the output.
root_instance_repeat (type=string, default=1, added 171024.01): if specified, this value will specify the replication number of the root instance in the output.
add_user_param_defines (type=boolean, default=false, added 171103.01): if specified, defines for any user-defined properties having name starting with js_ will be added to the jspec output (as typedef param name...).
keep_fset_hierarchy (type=boolean, default=false, added 180201.01): if specified, fieldset hierarchy will be included in jspec output. By default, fieldset/fieldstruct hierarchy is collapsed into field output with field names prefixed by their fieldset/fieldstruct instance hierarchy.
root_component_is_instanced (type=boolean, default=true): if false, the root rdl component will be output as a component definition rather than an instance.
output_jspec_attributes (type=boolean, default=false): if true, jspec-specified attributes will be output as rdl js_attributes properties. This allows jspec attributes to be retained in a js->rdl->js conversion.
no_root_enum_defs (type=boolean, default=false): if true, enum components defined at root level will not be included in rdl output.
is_mem_threshold (type=int, default=1000): If specified, will cause registers replicated more than the specified number of times to be modeled as uvm_vregs and uvm_mem to conserve simulation runtime memory.
suppress_no_category_warnings (type=boolean, default=false): If true, warning messages indicating a register has no category assigned will be inhibited.
include_address_coverage (type=boolean, default=false): If true, address coverage will be included in the generated UVM model.
max_reg_coverage_bins (type=int, default=128): If specified, coverage bins for replicated registers will be limited to the specified count.
reuse_uvm_classes (type=boolean, default=false): If specified, uvm block and register classes with similar properties (excluding parent/ancestor derived info) will be reused in the generated uvm model. This can significantly reduce the number of unique classes defined in the model (the class instance count remains the same).
skip_no_reset_db_update (type=boolean, default=true, added=170613.01): if true, the uvm_resource_db update of NO_REG_HW_RESET_TEST for fields with no defined reset will be bypassed. This improves uvm model build performance.
uvm_model_mode (type=[heavy|lite1|native], default=heavy, added 170710.01): Sets the type of uvm register model to be generated. If set to lite1, a lightweight model will be generated with no rdl property extensions and callbacks. The lite1 model only supports a subset of the heavy model api (primarily register read/write) and reduces runtime footprint for large designs where a simple (register read/write) api is sufficient. The native model uses only native uvm_reg classes, thus omitting the rdl extended classes of the heavy model, and also uses a uvm_reg_field instance for each register field unlike the lite1 model which has a single field data instance per register.
regs_use_factory (type=boolean, default=false, added 170727.01): if true, uvm registers will be created by and registered with the factory
use_numeric_uvm_class_names (type=boolean, default=false, added 180502.01): if true, model block and register class names will be created from a unique integer value, rather than the catenated instance path.
uvm_mem_strategy (value=[basic|block_wrapped|mimic_reg_api], default=block_wrapped, added 180502.01): sets the structure that will be used when modeling replicated register arrays identified as uvm_mem. if basic, a uvm_mem and uvm_vreg instance will be added to the parent (regfile) uvm_block. If block_wrapped, a uvm_block instance having the register instance name will be added to the parent (regfile) uvm_block and the uvm_mem and uvm_vreg instances will be wrapped in the new uvm_block. If mimic_reg_api, uvm_mem and uvm_vreg instances will be created same as the basic option, but in addition an array of relatively lightweight uvm_reg_mimic instances will be created that provide indirect access to the uvm_vreg using an api similar to an array of uvm_reg. Intent of mimic_reg_api is to minimize test sequence changes when moving a register array between uvm_reg and uvm_mem while getting at least some model footprint benefits when using the latter.
base_address_override (type=address, added 180606.01): If specified sets the base address in the generated uvmregs model. By default, the model base address is defined by the global base_address setting.
use_module_path_defines (type=boolean, default=true, added 181106.01): If true, defines will be created for setting root module hdl paths. If a generated uvmregs model is to be instanced multiple times in a bench, this parameter should be set to false and the set_rdl_address_map_hdl_path() method should be used to uniquely set the root hdl path in each block representing an addrmap (each having it's own rtl module).
display_external_regs (type=boolean, default=true): If true, external registers are included in output.
show_reg_type (type=boolean, default=true): If true, an internal/external indication will be shown for each reg. Inhibiting this indication can be helpful in some cases when diffing reglists generated from various inputs.
match_instance (type=string, default=null): If specified, output will only include registers with names containing the given string.
show_fields (type=boolean, default=false): If true, field info for each register will also be included in the output.
include_field_hw_info (type=boolean, default=true, added=170718.01): If true, xml output will include rdl field property info used for rtl generation.
generate_memory_map (type=boolean, default=true, added=230719.01): If true, generate an enum containing register addresses.
generate_bitfield (type=boolean, default=true, added=230719.01): If true, generate macros for extracting each register field.
generate_explicit_functions (type=boolean, default=false, added=230719.01): If true, add bits.h contents inline rather then using include.
At times, it is helpful to be able to set design properties outside of the rdl or jsec source definition. The annotation commands (set_regset_propety, set_reg_property, set_fieldset_property, set_field_property**) provide a means to modify properties on components or instances of the specified type with the specified name. Examples...
set_regset_property default uvmreg_prune = "true" components "assist_engine_1" // set a default property on all register set components having specified name
set_reg_property cppmod_prune = "true" instances "foo.bar.*" // set property on all register instances having specified path
set_fieldset_property use_new_interface = "true" instances "foo.blabla.*" // set property on all fieldset instances having specified path