Decoder and child region interface options - Juniper/open-register-design-tool GitHub Wiki
Decoder and child region interface options
images/sv_structure/if_types.png
- Example rdl showing use of different decoder interfaces
- Decoder interface IO descriptions
- external keyword info
Secondary uP interfaces
It is useful at times to be able to access some/all of the register space from multiple hosts. A secondary uP interface will be added to generated decoder logic if the secondary_decoder_interface is specified. Arbitration between primary and secondary interfaces is simple round-robin and currently atomic read-modify-write transactions are not supported on the uP interface protocols. Options are available to specify a different base address seen by the secondary interface as well as limit access by the secondary interface to a specified address range (see here).
images/sv_structure/sec_if.png
Assist Engine as a secondary uP interface
If secondary_decoder_interface = engine1 is specified, an assist state machine will be created on the secondary interface capable of generating a simple sequence of reads or writes. Intent is to provide offload of the uP when performing tasks such as: writing a number of address locations to a particular value, scrubbing sram data (rmw), or polling to capture the max/min value of a particular register while the primary uP interface is busy with other tasks. The engine has three primary modes: read-only, write_only, or read-modify-write, which is determined by the *_cfg_mode input signal. A sequence of transactions of the specified type is initiated by setting the *_cntl_start signal high. The sequence can be terminated after a specified number of transactions, upon reading a specified value, or via the *_cntl_force_stop signal. An attempt to access an out of range address location or a returned nack from the decoder will also terminate the sequence. Other inputs... tbd. Assist engine inputs can be controlled by external RTL or connected to generated register ports (rdl describing compatible control and status registers is written to stdout and can be embedded in an input rdl file to simplify this process).
