SoCKit HW Lab - ArrowElectronics/arrow-soc-workshops GitHub Wiki

Table of Contents

Overview

The Intel PSG SoC combines a Hard Processing System (HPS) and an FPGA on a single device. The HPS has dual core ARM Cortex-A9 MPUs and a host of peripherals such as DDR3 controllers, Ethernet MACs, SPI controllers and many more.

The FPGA portion of the device is tightly coupled through high performance bridges to the HPS. The designer can add peripherals they create or third-party IP to the FPGA and map it into the HPS. Thus, you have a flexible and very powerful solution.

This hardware lab provides answers to the following questions that a hardware developer might have:

  • How do I build a complete customized HPS SoC system?
  • How do I create an HPS in Platform Designer to realize a custom ARM SoC system with bridges to the FPGA?
  • How do I configure the HPS in Platform Designer to realize a unique set of HPS peripherals for a custom SoC system?
  • How do I use standard Platform Designer components to create a customized set of FPGA peripherals for my SoC system?
  • How do I use System Console to verify the peripherals in my SoC system are working properly?

The HPS is configured using Platform Designer, Intel PSG's SoC/FPGA IP integration tool. Configuration includes selecting DDR memory, determining clock frequencies and selecting which HPS peripherals your design will use. As such Platform Designer inherently has most of the information to satisfy the questions asked above.

Platform Designer is also used to define the HPS peripheral pin outs; Quartus is used to define the FPGA peripheral pin outs. These two Intel PSG FPGA development tools generate the files needed for the transfer of design information from the hardware to the software domain.

A portion of the hardware modules will create a set of handoff files that are required to build a preloader, a system register set (including FPGA registers), and the files required to create a Device Tree that will support any operating system.

For instance, the .socpinfo file will be used by the software designer to create a Device Tree which will in turn be utilized to provide an interface for the device drivers in Linux or other operating system.

Platform Designer creates the files required for Hardware to Software domain transfer:

The diagram below shows three main areas of transfer from the hardware to software domains.

  1. The files necessary to create a custom preloader
  2. The .svd file that describes the FPGA peripherals and is used by the DS-5 register function
  3. The sopcinfo file that describes all of the HPS devices selected in Platform Designer and also those custom peripherals added in the FPGA. These are used to build a device tree. The device tree is used by the Linux kernel to determine which device drivers to load at boot time.

Getting Started

  • Acquire the SocKit:
    If you don't already have a SocKit it can be purchased from Arrow here: Arrow's SocKit
  • This lab uses Quartus Lite version 19.1.
    If it is not already installed on your computer go to this link to download: Quartus Lite 19.1. Note that there is no cost for this version.
  • Install SoCKit Lab Files:
    • Create the folder C:\Intel PSG_trn on your PC
    • Download the lab files by following this link and selecting the Download button: SoCKIT_Materials_19.1.zip
    • Save to C:\Intel PSG_trn on your PC
    • Extract the SoCKIT_Materials_19.1.zip file to the default folder shown below.
    • The C:\Intel PSG_trn directory should now look like this:

Get the Cyclone V SoCKit ready for the Labs

Connect cables to the connectors shown in the diagram below. All cables are provided in your SoCKit.

  • Connect the micro or mini (Rev E) USB cable to the USB host connector on your laptop and to the USB Blaster II connector on the SoCKit.
  • Connect the Power Supply to the Power connector on the SoCKit. Do not power on the board at this time.

There are a few jumpers that require configuring before proceeding with the labs.

  • BOOTSEL[2..0] jumpers. These should be configured as "100" to select boot from SD card 3.3V
  • CLKSEL[1..0] jumpers. These should be configured as "00" for the slowest HPS peripheral clock speed option.

Ensure that the jumpers are configured as indicated below.

Modify the default MSEL bit settings. The board needs to be set to configure in the FPPx32, fast, compressed mode. This will allow u-boot to configure the FPGA.

  • SW6 is located on the bottom side of the SoCKit.
  • Please change MSEL[0:4] to 01010.

Verify that the JTAG chain is correctly configured. The JTAG chain switch is located to the right of the green audio connector.

  • HSMC_EN should be disabled (left position) and the HPS_EN should be enabled (right position).

Verify the USB Blaster II Device Driver is Installed

  • Turn your SoCKit on by pressing the red power button next to the power connector.
  • Open a NIOS II 19.1 Command Shell
    Select the Windows Start button then go to: Intel PSG 19.1.0.211 Lite Edition -> NIOS II EDS 19.1.0.211 -> NIOS II 19.1 Command Shell
  • Type jtagconfig at the prompt and press enter.
  • If the jtagconfig command fails (“No JTAG hardware available”message), then the driver is not installed.
  • Follow the steps in this document to install the driver USB BlasterInstall. Go to section 3.1. Installing the Intel FPGA Download Cable Driver on Windows.